![](http://datasheet.mmic.net.cn/Altera/EP1S80F1020C5N_datasheet_97268/EP1S80F1020C5N_242.png)
4–62
Altera Corporation
Stratix Device Handbook, Volume 1
January 2006
Timing Model
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
(1)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2)
VCCINT is 1.42-V unless otherwise specified.
VCCIO
GND
OUTPUT
GND
R
T
V
TT
R
S
C
L
Output
Buffer
Single-Ended Outputs
V
MEAS
GND
R
UP
VCCIO
R
DN
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2)
I/O Standard
Loading and Termination
Measurement
Point
RUP
Ω
RDN
Ω
RS
Ω
RT
Ω
VCCIO
(V)
VTT
(V)
CL
(pF)
VMEAS
3.3-V LVTTL
–
0
–
2.950
2.95
10
1.500
2.5-V LVTTL
–
0
–
2.370
2.37
10
1.200
1.8-V LVTTL
–
0
–
1.650
1.65
10
0.880
1.5-V LVTTL
–
0
–
1.400
1.40
10
0.750
3.3-V LVCMOS
–
0
–
2.950
2.95
10
1.500
2.5-V LVCMOS
–
0
–
2.370
2.37
10
1.200
1.8-V LVCMOS
–
0
–
1.650
1.65
10
0.880
1.5-V LVCMOS
–
0
–
1.400
1.40
10
0.750
3.3-V GTL
–
0
25
2.950
1.14
30
0.740
2.5-V GTL
–
0
25
2.370
1.14
30
0.740
3.3-V GTL+
–
0
25
2.950
1.35
30
0.880
2.5-V GTL+
–
0
25
2.370
1.35
30
0.880
3.3-V SSTL-3 Class II
–
25
2.950
1.25
30
1.250