Altera Corporation
4–101
January 2006
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tJITTER
Period jitter for DIFFIO clock out
(6)ps
tLOCK
Time required for PLL to acquire lock
10
100
μs
m
Multiplication factors for m counter
(7)1
32
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
1
32
Integer
tARESET
Minimum pulse width on areset
signal
10
ns
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fIN
CLKIN
10
460
MHz
fINPFD
Input frequency to PFD
10
500
MHz
fOUT
Output frequency for internal global or
9.375
420
MHz
fOUT_DIFFIO
Output frequency for external clock
driven out on a differential I/O data
channel
MHz
fVCO
VCO operating frequency
300
700
MHz
tINDUTY
CLKIN
duty cycle
40
60
%
tINJITTER
Period jitter for CLKIN pin
±200
ps
tDUTY
Duty cycle for DFFIO 1
45
55
%
tJITTER
Period jitter for DIFFIO clock out
(6)ps
tLOCK
Time required for PLL to acquire lock
10
100
μs
m
Multiplication factors for m counter
(7)1
32
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
1
32
Integer
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit