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參數(shù)資料
| 型號： | EP1S30B1508C5ES |
| 廠商： | Altera Corporation |
| 英文描述： | Stratix Device Family Data Sheet |
| 中文描述： | Stratix系列器件數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 116/290頁 |
| 文件大?。?/td> | 3559K |
| 代理商： | EP1S30B1508C5ES |
2–92
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
PLLs & Clock Networks
bandwidth is tuned by varying the charge pump current, loop filter
resistor value, high frequency capacitor value, and
m
counter value. You
can manually adjust these values if desired. Bandwidth is programmable
from 200 kHz to 1.5 MHz.
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). Differential SSTL and HSTL outputs
are implemented using 2 single-ended output buffers which are
programmed to have opposite polarity. In Quartus II software, simply
assign the appropriate differential I/O standard and the software will
implement the inversion. See
Figure 2–55
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1S30B1508C6ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix Device Family Data Sheet |
| EP1S30B1508C7ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix Device Family Data Sheet |
| EP1S30B1508I5ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix Device Family Data Sheet |
| EP1S30B1508I6ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix Device Family Data Sheet |
| EP1S30B1508I7ES | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix Device Family Data Sheet |
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