參數(shù)資料
型號： EP1S25F672C7N
廠商： Altera
文件頁數(shù)： 724/864頁
文件大?。?/td> 0K
描述： IC STRATIX FPGA 25K LE 672-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準包裝： 20
系列： Stratix®
LAB/CLB數(shù)： 2566
邏輯元件/單元數(shù)： 25660
RAM 位總計： 1944576
輸入/輸出數(shù)： 473
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-BGA（27x27）
其它名稱： 544-1858
EP1S25F672C7N-ND
11–32
Altera Corporation
Stratix Device Handbook, Volume 2
July 2005
Configuration Schemes
be monitored, reading the state of the configuration data by strobing nRS
low saves a system I/O port. Do not drive data onto the data bus while
nRS
is low because it causes contention on DATA7. If the nRS pin is not
used to monitor configuration, you should tie it high. To simplify
configuration, the microprocessor can wait for the total time of
tBUSY (max) + tRDY2WS + tW2SB before sending the next data bit.
After configuration, the nCS, CS, nRS, nWS, and RDYnBSY pins act as user
I/O pins. However, if the PPA scheme is chosen in the Quartus II
software, these I/O pins are tri-stated by default in user mode and should
be driven by the microprocessor. To change the default settings in the
Quartus II software, select Device & Pin Option (Compiler Setting
menu).
If the Stratix or Stratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on, the Stratix or Stratix GX device releases nSTATUS after a
reset time-out period. After nSTATUS is released, the microprocessor can
reconfigure the Stratix or Stratix GX device. At this point, the
microprocessor does not need to pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The microprocessor must
monitor the nSTATUS pin to detect errors and the CONF_DONE pin to
determine when programming completes (CONF_DONE goes high one
byte early in parallel mode). If the microprocessor sends all configuration
data and starts initialization but CONF_DONE is not asserted, the
microprocessor must reconfigure the Stratix or Stratix GX device.
By default, the INIT_DONE is disabled. You can enable the INIT_DONE
output by turning on the Enable INIT_DONE output option in the
Quartus II software. If you do not turn on the Enable INIT_DONE
output
option in the Quartus II software, you are advised to wait for the
maximum value of tCD2UM (see Table 11–10) after the CONF_DONE signal
goes high to ensure the device has been initialized properly and that it has
entered user mode.
During configuration and initialization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure that CLKUSR continues toggling during the time
nSTATUS
is low (maximum of 40
μs).
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參數(shù)描述
EP1S25F672C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I 2566 LABs 473 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1S25F672C8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I 2566 LABs 473 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1S25F672I7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I 2566 LABs 473 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1S25F672I7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I 2566 LABs 473 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1S25F780C5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I 2566 LABs 597 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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