
Altera Corporation
4–65
January 2006
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Figure 4–8 shows the measurement setup for output disable and output
enable timing. The TCHZ stands for clock to high Z time delay and is the
same as TXZ. The TCLZ stands for clock to low Z (driving) time delay and
is the same as TZX.
Figure 4–8. Measurement Setup for TXZ and TZX
3.3-V CTT
–
25
50
3.600
1.650
30
1.650
(1)
Input measurement point at internal node is 0.5 × VCCINT.
(2)
Output measuring point for data is VMEAS. When two values are given, the first is the measurement point on the
rising edge and the other is for the falling edge.
(3)
Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the I/O buffer.
(4)
The first value is for the output rising edge and the second value is for the output falling edge. The hyphen (-)
indicates infinite resistance or disconnection.
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination
Measurement
Point
RUP
Ω
RDN
Ω
RS
Ω
RT
Ω
VCCIO
(V)
VTT
(V)
CL
(pF)
VMEAS
200mV
CLK
OUT
T CHZ
T CLZ
V
T =1.5V
C TOTAL=10pF
R =50
Ω