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    • 參數(shù)資料
    型號(hào)： EP1K50FI256-1F
    英文描述： Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40&deg;C to 85&deg;C; Package: 10-DFN
    中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
    文件頁(yè)數(shù)： 43/86頁(yè)
    文件大?。?/td> 1263K
    代理商： EP1K50FI256-1F
    48
    Altera Corporation
    ACEX 1K Programmable Logic Device Family Data Sheet
    Notes to tables:
    (1)
    (2)
    Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
    less than 100 mA and periods shorter than 20 ns.
    (3)
    Numbers in parentheses are for industrial-temperature-range devices.
    (4)
    Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
    (5)
    All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
    powered.
    (6)
    Typical values are for TA = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.
    (7)
    These values are specified under the ACEX 1K Recommended Operating Conditions shown in Table 19 on page 46.
    (8)
    The ACEX 1K input buffers are compatible with 2.5-V, 3.3-V (LVTTL and LVCMOS), and 5.0-V TTL and CMOS
    signals. Additionally, the input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship
    shown in Figure 22.
    (9)
    The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
    (10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
    as well as output pins.
    (11) This value is specified for normal device operation. The value may vary during power-up.
    (12) This parameter applies to -1 speed grade commercial temperature devices and -2 speed grade industrial
    temperature devices.
    (13) Pin pull-up resistance values will be lower if the pin is driven higher than VCCIO by an external source.
    (14) Capacitance is sample-tested only.
    Table 21. ACEX 1K Device Capacitance
    Symbol
    Parameter
    Conditions
    Min
    Max
    Unit
    CIN
    Input capacitance
    VIN = 0 V, f = 1.0 MHz
    10
    pF
    CINCLK
    Input capacitance on
    dedicated clock pin
    VIN = 0 V, f = 1.0 MHz
    12
    pF
    COUT
    Output capacitance
    VOUT = 0 V, f = 1.0 MHz
    10
    pF
    相關(guān)PDF資料
    PDF描述
    EP1K50FI256-1P Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40&deg;C to 85&deg;C; Package: 10-DFN
    EP1K50FI256-1X Field Programmable Gate Array (FPGA)
    EP1K50FI256-2DX Field Programmable Gate Array (FPGA)
    EP1K50FI256-2P Field Programmable Gate Array (FPGA)
    EP1K50FI256-2X Field Programmable Gate Array (FPGA)
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    EP1K50FI256-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
    EP1K50FI256-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
    EP1K50FI256-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
    EP1K50FI256-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
    EP1K50FI256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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