參數(shù)資料
型號(hào)： EP1C6T400C7
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 49/94頁(yè)
文件大小： 1138K
代理商： EP1C6T400C7
Altera Corporation
49
Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 31. Control Signal Selection per IOE
In normal bidirectional operation, the designer can use the input register
for input data requiring fast setup times. The input register can have its
own clock input and clock enable separate from the OE and output
registers. The output register can be used for data requiring fast clock-to-
output performance. The OE register is available for fast clock-to-output
enable timing. The OE and output register share the same clock source
and the same clock enable source from the local interconnect in the
associated LAB, dedicated I/O clocks, or the column and row
interconnects.
Figure 32
shows the IOE in bidirectional configuration.
clk_out
ce_in
clk_in
ce_out
aclr/preset
sclr/preset
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
oe
io_coe
io_caclr
Local
Interconnect
io_csclr
io_cce_out
io_cce_in
io_cclk
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