參數(shù)資料
型號(hào): EP1C6T324I8
廠商: Altera Corporation
英文描述: Cyclone FPGA Family
中文描述: 氣旋FPGA系列
文件頁(yè)數(shù): 26/94頁(yè)
文件大小: 1138K
代理商: EP1C6T324I8
26
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge clocking
to shift the data in one clock cycle.
Figure 14
shows the M4K memory
block in the shift register mode.
Figure 14. Shift Register Memory Configuration
m
-Bit Shift Register
w
w
m
-Bit Shift Register
m
-Bit Shift Register
m
-Bit Shift Register
w
w
w
w
w
w
w
×
m
×
n
Shift Register
n Number
of Taps
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