參數(shù)資料
型號: EP1C6T240C7ES
廠商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 氣旋的FPGA系列數(shù)據(jù)手冊
文件頁數(shù): 49/104頁
文件大?。?/td> 763K
代理商: EP1C6T240C7ES
Altera Corporation
January 2007
2–43
Preliminary
I/O Structure
The pin's datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks,
io_clk[5..0]
, provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page 2–29
).
Figure 2–30
illustrates the signal paths through the I/O block.
Figure 2–30. Signal Path through the I/O Block
Each IOE contains its own control signal selection for the following
control signals:
oe
,
ce_in
,
ce_out
,
aclr
/
preset
,
sclr
/
preset
,
clk_in
, and
clk_out
.
Figure 2–31
illustrates the control signal
selection.
Row or Column
io_clk[5..0]
io_datain
comb_io_datain
io_dataout
io_coe
oe
ce_in
ce_out
io_cce_in
aclr/preset
io_cce_out
sclr
io_caclr
clk_in
io_cclk
clk_out
dataout
Data and
Control
Signal
Selection
IOE
To Logic
Array
From Logic
Array
To Other
IOEs
io_csclr
相關(guān)PDF資料
PDF描述
EP1C6T240C8ES Cyclone FPGA Family Data Sheet
EP1C6T240I6ES Cyclone FPGA Family Data Sheet
EP1C6T240I7ES Cyclone FPGA Family Data Sheet
EP1C6T240I8ES Cyclone FPGA Family Data Sheet
EP1C6T256C6ES Cyclone FPGA Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1F 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
EP1F-B3G1 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
EP1FB3G1S 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole
EP1F-B3G1T 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY
EP1F-B3G1TT 制造商:NEC 制造商全稱:NEC 功能描述:HIGH HEAT RESISTIVITY