參數(shù)資料
型號(hào)： EP1C6Q144I7ES
廠商： Altera Corporation
英文描述： Cyclone FPGA Family Data Sheet
中文描述： 氣旋的FPGA系列數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù)： 39/104頁(yè)
文件大?。?/td> 763K
代理商： EP1C6Q144I7ES
Altera Corporation
January 2007
2–33
Preliminary
Global Clock Network & Phase-Locked Loops
Table 2–6
shows the PLL features in Cyclone devices.
Figure 2–25
shows
a Cyclone PLL.
Figure 2–25. Cyclone PLL
Note (1)
Notes to
Figure 2–25
:
(1)
The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
(2)
LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the
CLK0
pin’s secondary
function is
LVDSCLK1p
and the
CLK1
pin’s secondary function is
LVDSCLK1n
. For PLL 2, the
CLK2
pin’s secondary
function is
LVDSCLK2p
and the
CLK3
pin’s secondary function is
LVDSCLK2n
.
(3)
PFD: phase frequency detector.
Table 2–6. Cyclone PLL Features
Feature
PLL Support
Clock multiplication and division
m
/(
n
×
post-scale counter)
(1)
Down to 125-ps increments
(2)
,
(3)
Phase shift
Programmable duty cycle
Yes
N
umber of internal clock outputs
2
N
umber of external clock outputs
One differential or one single-ended
(4)
Notes to
Table 2–6
:
(1)
The
m
counter ranges from 2 to 32. The
n
counter and the post-scale counters
range from 1 to 32.
(2)
The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
(3)
For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
(4)
The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Charge
Pump
VCO
PFD
(3)
Loop
Filter
CLK0 or
LVDSCLK1p
(2)
CLK1 or
LVDSCLK1n
(2)
÷
n
÷
m
Δ
t
Δ
t
Global clock
Global clock
I/O buffer
÷g0
÷g1
÷e
VCO Phase Selection
SelecOutput Port
Post-Scale
Counters
相關(guān)PDF資料
PDF描述
EP1C6Q144I8ES Cyclone FPGA Family Data Sheet
EP1C6Q240C6ES Cyclone FPGA Family Data Sheet
EP1C6Q240C7ES Cyclone FPGA Family Data Sheet
EP1C6Q400I8 Cyclone FPGA Family
EP1C4T100I6 Cyclone FPGA Family
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EP1C6Q240C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C8 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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