參數(shù)資料
型號(hào)： EP1C6Q100I6
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁(yè)數(shù)： 80/94頁(yè)
文件大?。?/td> 1138K
代理商： EP1C6Q100I6
80
Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Table 48
shows the external I/O timing parameters when using global
clock networks.
Notes to
Table 48
:
(1)
These timing parameters are sample-tested only.
(2)
These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
Table 48. Cyclone Global Clock External I/O Timing Parameters
Notes (1)
,
(2)
Symbol
Parameter
Conditions
t
INSU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
Hold time for input or bidirectional pin using IOE input
register with global clock fed by
CLK
pin
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by
CLK
pin
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by
CLK
pin
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by
CLK
pin
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock enhanced PLL with default
phase setting
Synchronous column IOE output enable register to output
pin disable delay using global clock fed by enhanced PLL
with default phase setting
Synchronous column IOE output enable register to output
pin enable delay using global clock fed by enhanced PLL
with default phase setting
t
INH
t
OUTCO
C
LOAD
= 10 pF
t
XZ
C
LOAD
= 10 pF
t
ZX
C
LOAD
= 10 pF
t
INSUPLL
t
INHPLL
t
OUTCOPLL
C
LOAD
= 10 pF
t
XZPLL
C
LOAD
= 10 pF
t
ZXPLL
C
LOAD
= 10 pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1C6Q240C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C7N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6Q240C8 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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