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參數資料
| 型號： | EP1C4T100C8 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁數： | 11/94頁 |
| 文件大小： | 1138K |
| 代理商： | EP1C4T100C8 |
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Altera Corporation
11
Preliminary Information
Cyclone FPGA Family Data Sheet
addnsub Signal
The LE’s dynamic adder/subtractor feature saves logic resources by using
one set of LEs to implement both an adder and a subtractor. This feature
is controlled by the LAB-wide control signal
addnsub
. The
addnsub
signal sets the LAB to perform either A + B or A
B. The LUT computes
addition; subtraction is computed by adding the two’s complement of the
intended subtractor. The LAB-wide signal converts to two’s complement
by inverting the B bits within the LAB and setting carry-in = 1 to add one
to the least significant bit (LSB). The LSB of an adder/subtractor must be
placed in the first LE of the LAB, where the LAB-wide
addnsub
signal
automatically sets the carry-in to 1. The Quartus II Compiler
automatically places and uses the adder/subtractor feature when using
adder/subtractor parameterized functions.
LE Operating Modes
The Cyclone LE can operate in one of the following modes:
■
■
Normal mode
Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available
inputs to the LE
the four data inputs from the LAB local interconnect,
carry-in0
and
carry-in1
from the previous LE, the LAB carry-in
from the previous carry-chain LAB, and the register chain
connection
are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous
clear, asynchronous preset/load, synchronous clear, synchronous load,
and clock enable control for the register. These LAB-wide signals are
available in all LE modes. The
addnsub
control signal is allowed in
arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, the designer can
also create special-purpose functions that specify which LE operating
mode to use for optimal performance.
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| EP1C6F100C8 | Cyclone FPGA Family |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP1C6F256C6 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6F256C6N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6F256C7 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6F256C7N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1C6F256C8 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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