參數(shù)資料
型號： EP1C4Q400I7
廠商： Altera Corporation
英文描述： Cyclone FPGA Family
中文描述： 氣旋FPGA系列
文件頁數(shù)： 1/94頁
文件大小： 1138K
代理商： EP1C4Q400I7
Altera Corporation
1
Cyclone
FPGA Family
March 2003, ver. 1.1
Data Sheet
DS-CYCLONE-1.1
Introduction
Preliminary
Information
The Cyclone
TM
field programmable gate array family is based on a 1.5-V,
0.13-
μ
m, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
Features...
■
■
■
■
■
■
■
2,910 to 20,060 LEs, see
Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
MegaCore
functions and Altera Megafunctions Partners
Program (AMPP
SM
) megafunctions
■
■
■
Note to
Table 1
:
(1)
This parameter includes global clock pins.
Table 1. Cyclone Device Features
Feature
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
LEs
M4K RAM blocks (128
×
36 bits)
Total RAM bits
PLLs
Maximum user I/O pins
(1)
2,910
13
59,904
1
104
4,000
17
78,336
2
301
5,980
20
92,160
2
185
12,060
52
239,616
2
249
20,060
64
294,912
2
301
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EP1C6F256C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6F256C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6F256C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6F256C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1C6F256C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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