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| 型號(hào)： | Enhanced Am486 dx2 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁(yè)數(shù)： | 53/69頁(yè) |
| 文件大?。?/td> | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
53
PRELIMINARY
onto the stack. If the offset of the interrupted procedure
is greater than 64 Kbytes, it is not possible for the in-
terrupt/exception handler to return control to that pro-
cedure. (One work-around is to perform software
adjustment of the return address on the stack.)
The SMBASE Relocation feature affects the way the
CPU returns from an interrupt or exception during an
SMI handler.
4)
Note:
The execution of an IRET instruction enables
Non-Maskable Interrupt (NMI) processing.
7.9.3
Halt during SMM
HALT should not be executed during SMM, unless in-
terrupts have been enabled. Interrupts are disabled on
entry to SMM. INTR and NMI are the only events that take
the CPU out of HALT within SMM.
7.9.4
Relocating SMRAM to an Address above
1 Mbyte
Within SMM (or Real mode), the segment base registers
can be updated only by changing the segment register.
The segment registers contain only 16 bits, which
allows
only 20 bits to be used for a segment base address (the
segment register is shifted left 4 bits to
determine the seg-
ment base address). If SMRAM is relocated to an address
above 1 Mbyte, the segment registers can no longer be
initialized to point to SMRAM.
These areas can still be accessed by using address
override prefixes to generate an offset to the correct
address. For example, if the SMBASE has been relo-
cated immediately below 16M, the DS and ES registers
are still
initialized to 0000 0000h. Data in SMRAM can still
be accessed by using 32-bit displacement registers:
move esi,OOFFxxxxh;64K segment immediately
below 16M
move ax,ds:[esi]
8
TEST REGISTERS 4 AND 5
MODIFICATIONS
The Cache Test Registers for the Enhanced Am486 mi-
croprocessor are the same test registers (TR3, TR4,
and TR5) provided in earlier Am486DX and DX2 micro-
processors. TR3 is the cache test data register. TR4,
the cache test status register, and TR5, the cache test
control register, operate together with TR3.
If WB/WT meets the necessary setup timing and is sam-
pled Low on the falling edge of RESET, the processor
is placed in write-through mode and the test register
function is identical to the earlier Am486 microproces-
sors. If WB/WT meets the necessary setup timing and
is sampled High on the falling edge of RESET, the pro-
cessor is placed in write-back mode and the test regis-
ters TR4 and TR5 are modified to support the added
write-back cache functionality. Tables 17 and 18 show
the individual bit functions of these registers. Sections
8.1 and 8.2 provide a detailed description of the field
functions.
Note:
TR3 has the same functions n both write-through
and write-back modes.These functions are identical to
the TR3 register functions provided by earlier Am486
microprocessors.
8.1
TR4 Definition
This section includes a detailed description of the bit
fields defined for TR4.
Note:
Bits listed in Tables 17 as Reserved or Not used
are not included in these descriptions.
n
Tag (bits 31–11): Read/Write, always available in
write-through mode. Available only when EXT=0 in
TR5 in write-back mode. For a cache write, this is
the tag that specifies the address in memory. On a
cache look-up, this is tag for the selected entry in the
cache.
Table 17. Test Register (TR4)
31
30–29
28
27–26
25–24
23–22
21–20
19
18
17
16 15–11
10
9–7
6–3
2–0
Tag
Valid
LRU
Valid
(rd)
Not
used
Not
used
STn
Rsvd.
ST3
ST2
ST1
ST0
Reserved
Not
used
Valid
LRU
Valid
(rd)
Not
used
Table 18. Test Register (TR5)
31–20
19
18–17
16
15–11
10–4
3–2
1–0
Write-Back
Not used
Ext
Set State
Reserved
Not used
Index
Entry
Control
Write-Through
Note:
The values of STn, ST3–ST0, and Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared
Not used
Index
Entry
Control
EXT = 0
EXT = 1
Note:
If EXT = 0, TR4 has the standard 486 processor definition for write-through cache.
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| EO12 | IRDA INFRARED TRANSCEIVER |
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