參數(shù)資料
型號(hào)： EN29LV512-90TC
廠商： Electronic Theatre Controls, Inc.
英文描述： 512 Kbit (64K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory
中文描述： 512千位（64K的× 8位）統(tǒng)一部門(mén)，3.0伏的CMOS只閃存
文件頁(yè)數(shù)： 12/35頁(yè)
文件大小： 403K
代理商： EN29LV512-90TC
This Data Sheet may be revised by subsequent versions 2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2004/01/05
EN29LV512
an attempt to read the device will produce the true data last written to DQ7. For the embedded
Programming,
DATA
polling is valid after the rising edge of the fourth
WE
or
CE
pulse in the four-
cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
DATA
polling is valid after the rising edge of the sixth
W E
or
CE
pulse in the six-cycle sequence. For Sector Erase,
DATA
polling is valid after the last
rising edge of the sector erase
WE
or
CE
pulse.
DATA
Polling must be performed at any address within a sector that is being programmed or
erased and not a protected sector. Otherwise,
DATA
polling may give an inaccurate result if the
address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable (
OE
) is low. This means that the device is driving status information on DQ7 at
one instant of time and valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
DATA
Polling (DQ7) is shown on Flowchart 5. The
DATA
Polling (DQ7) timing
diagram is shown in Figure 8.
DQ6: Toggle Bit I
The EN29LV512 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling
OE
or
CE
) will result in DQ6 toggling between “zero” and “one”. Once
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth
WE
pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is
valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after
the last rising edge of the Sector Erase
W E
pulse.
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2
μ
s, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100
μ
s. The chip will then return to the read
mode without changing data in all protected blocks.
Toggling either
CE
or
OE
will cause DQ6 to toggle.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9
.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the
program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a
1 when the device has successfully completed its operation and has returned to read mode, the user
must check again to see if the DQ6 is toggling after detecting a “1” on DQ5.
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