參數(shù)資料
型號(hào)： EN29LV400AT-55RTCP
廠商： Electronic Theatre Controls, Inc.
英文描述： Replaced by PTH04070W :
中文描述： 4兆位（為512k × 8位/ 256 × 16位）閃存引導(dǎo)扇區(qū)閃存，CMOS 3.0伏，只
文件頁(yè)數(shù)： 10/41頁(yè)
文件大?。?/td> 771K
代理商： EN29LV400AT-55RTCP
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t
acc
+ 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. ICC
4
in the DC Characteristics table represents the automatic sleep more
current specification.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low V
CC
Write Inhibit
When Vcc is less than V
LKO
, the device does not accept any write cycles. This protects data during
Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V
LKO
. The
system must provide the proper signals to the control pins to prevent unintentional writes when Vcc
is greater than V
LKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a
write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#
are all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE# = V
IL
, WE# = V
IL
and OE# = V
IH
, the device will not accept commands on the rising edge of
WE#.
This Data Sheet may be revised by subsequent versions 2005 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2005/01/07
EN29LV400A
相關(guān)PDF資料
PDF描述
EN29LV400AT-55RTI Replaced by PTH04070W :
EN29LV400AT-70TC Replaced by PTH04070W :
EN29LV400AT-70TCP Replaced by PTH04070W :
EN29LV400AT-70TI Replaced by PTH04070W :
EN29LV400AT-70TIP Replaced by PTH04070W :
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EN29LV400AT-70TCP 制造商:EON SILICON SOLUTION INC 功能描述:4 Mb PAR NOR 512Kx8bit/256Kx16bit 3V 48-TSOP
EN29LV800AB-70TC 制造商:Eon Silicon Solution Inc 功能描述:
EN29LV800BB-70TCP 制造商:EON SILICON SOLUTION INC 功能描述:EN29LV800B Series, 8 Mbit 70 NS 48 TSOP 3 V Bottom Boot Sector NOR Flash
EN29LV800CT-70TIP 制造商:EON SILICON SOLUTION INC 功能描述:8mb TSOP 70ns nor flash
EN29SL400B-90BIP 制造商:EON SILICON SOLUTION INC 功能描述:EN29SL400 Series, 4 Mbit 90 NS 48 FBGA 1.8 V Bottom Boot Sector NOR Flash
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