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參數資料
| 型號： | EN25P40-75VIP |
| 廠商： | Eon Silicon Solution Inc. |
| 元件分類： | FLASH |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統一部門，串行閃存 |
| 文件頁數： | 10/31頁 |
| 文件大?。?/td> | 441K |
| 代理商： | EN25P40-75VIP |
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Table 6. Status Register Bit Locations
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2006/12/25
EN25P40
The status and control bits of the Status Register are as follows:
BUSY bit.
The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is
set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if,
both Block Protect (BP2, BP1, BP0) bits are 0.
Reserved bit.
Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0
for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register.
Doing this will ensure compatibility with future devices.
SRP bit.
The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be
put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write
Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1,
BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
相關PDF資料 |
PDF描述 |
|---|---|
| EN25P40 | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50GC | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50GCP | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50GI | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50GIP | 4 Mbit Uniform Sector, Serial Flash Memory |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EN25P64 | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:64 Megabit Uniform Sector, Serial Flash Memory |
| EN25P64-100FI | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:64 Megabit Uniform Sector, Serial Flash Memory |
| EN25P64-100FIP | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:64 Megabit Uniform Sector, Serial Flash Memory |
| EN25P64-75FI | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:64 Megabit Uniform Sector, Serial Flash Memory |
| EN25P64-75FIP | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:64 Megabit Uniform Sector, Serial Flash Memory |
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