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參數(shù)資料
| 型號： | EN25P40-50VC |
| 廠商： | Eon Silicon Solution Inc. |
| 元件分類： | FLASH |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 441K |
| 代理商： | EN25P40-50VC |
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SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2006/12/25
EN25P40
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device
is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the
devices power consumption will be at standby levels unless an internal erase, program or status
register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used
in conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status
Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
Pin Name
CLK
Serial Clock Input
DI
Serial Data Input
DO
Serial Data Output
CS#
Chip Enable
WP#
Write Protect
HOLD#
Hold Input
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
相關PDF資料 |
PDF描述 |
|---|---|
| EN25P40-50VCP | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50VI | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50VIP | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-75GC | 4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-75GCP | 4 Mbit Uniform Sector, Serial Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EN25P40-50VCP | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50VI | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-50VIP | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-75GC | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:4 Mbit Uniform Sector, Serial Flash Memory |
| EN25P40-75GCP | 制造商:EON 制造商全稱:Eon Silicon Solution Inc. 功能描述:4 Mbit Uniform Sector, Serial Flash Memory |
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