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參數(shù)資料
| 型號： | EM78P5830AA |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 8-BIT MICRO-CONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 17/43頁 |
| 文件大?。?/td> | 396K |
| 代理商： | EM78P5830AA |
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EM785830AA
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit0
(RAM_B0).
PAGE2 : (undefined) not allowed to use
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
3
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
7
6
5
4
3
0
PLLEN
CLK2
CLK1
CLK0
R/W-0
R/W-0
R/W
R/W
R/W
Bit 0(WDTEN) : Watch dog control bit
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1
disable/enable
Bit 1~Bit 2 : Unused, these 2 bits are not allowed to use.
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
1
0
0
0
32.768kHz
1
0
0
1
32.768kHz
1
0
1
0
32.768kHz
1
0
1
1
32.768kHz
1
1
0
0
32.768kHz
1
1
0
1
32.768kHz
1
1
1
0
32.768kHz
1
1
1
1
Can’t allowed to use
0
don’t care don’t care don’t care
32.768kHz
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1
disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
447.8293kHz ~14.3MHz
2
1
0
R/W-0
R/W-0
R/W-0
2
X
-
1
X
-
0
WDTEN
R/W-0
MAIN clock
447.829kHz
895.658kHz
1.791MHz
3.582MHz
7.165MHz
10.747MHz
14.331MHz
CPU clock
447.829kHz (Normal mode)
895.658kHz (Normal mode)
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
10.747MHz (Normal mode)
14.331MHz (Normal mode)
don’t care
32.768kHz (Green mode)
Sub-clock
32.768kHz
switch
0
1
System
clock
PLL circuit
ENPLL
CLK2 ~ CLK0
Fig.7 The relation between 32.768kHz and PLL
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