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參數(shù)資料
| 型號： | EM78P451 |
| 英文描述： | Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| 中文描述： | 8位微控制器的通用產(chǎn)品[英文] |
| 文件頁數(shù)： | 4/52頁 |
| 文件大?。?/td> | 1287K |
| 代理商： | EM78P451 |
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EM78P451
OTP ROM
This specification is subject to change without prior notice.
2002/03/01
12
"1" means interrupt request, "0" means non-interrupt.
R3F can be cleared by instruction, but cannot be set by instruction.
IOCF is the interrupt mask register.
Note that to read R3F will result to "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
Internal data transfer, or instruction operand holding.
A non-addressable register.
2. CONT (Control Register)
7
6
5
4
3
2
1
0
/PHEN
/INT
-
PAB
PSR2
PSR1
PSR0
Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled.
1: The pull-high function is disabled.
Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction.
0: interrupt masked by the DISI instruction.
1: interrupt enabled by the ENI or RETI instruction.
Bit4, 5 Not used, and to be read as “0”.
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
1:2
1:1
0
1
1:4
1:2
0
1
0
1:8
1:4
1
1:16
1:8
1
0
1:32
1:16
1
0
1
1:64
1:32
1
0
1:128
1:64
1
1:256
1:128
Bits 0~3, and 7 of the CONT register are readable and writable.
3. IOC5 ~ IOC9 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
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