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EM78869
8-Bit RISC Type Microprocessor
28 of 34
07.12.2004 (V1.0)
This specification is subject to change without further notice.
INSTRUCTION
BINARY
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000
0000
NOP
No Operation
None
0 0000 0000 0001
0001
DAA
Decimal Adjust A
A
→
CONT
0
→
WDT, Stop oscillator
0
→
WDT
A
→
IOCR
C
0 0000 0000 0010
0002
CONTW
None
0 0000 0000 0011
0003
SLEP
T, P
0 0000 0000 0100
0004
WDTC
T, P
None
1
0 0000 0000 rrrr
000r
IOW R
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
[Top of Stack]
→
PC
[Top of Stack]
→
PC,
Enable Interrupt
CONT
→
A
IOCR
→
A
R2+A
→
R2,
Bits 8~9 of R2 unchanged
A
→
R
0
→
A
0
→
R
R-A
→
A
R-A
→
R
R-1
→
A
R-1
→
R
A
∨
R
→
A
A
∨
R
→
R
A & R
→
A
A & R
→
R
A
⊕
R
→
A
A
⊕
R
→
R
A + R
→
A
A + R
→
R
R
→
A
R
→
R
2
/R
→
A
None
0 0000 0001 0010
0012
RET
None
0 0000 0001 0011
0013
RETI
None
0 0000 0001 0100
0014
CONTR
None
None
1
0 0000 0001 rrrr
001r
IOR R
0 0000 0010 0000
0020
TBL
Z, C, DC
0 0000 01rr rrrr
00rr
MOV R,A
None
0 0000 1000 0000
0080
CLRA
Z
0 0000 11rr rrrr
00rr
CLR R
Z
0 0001 00rr rrrr
01rr
SUB A,R
Z, C, DC
0 0001 01rr rrrr
01rr
SUB R,A
Z, C, DC
0 0001 10rr rrrr
01rr
DECA R
Z
0 0001 11rr rrrr
01rr
DEC R
Z
0 0010 00rr rrrr
02rr
OR A,R
Z
0 0010 01rr rrrr
02rr
OR R,A
Z
0 0010 10rr rrrr
02rr
AND A,R
Z
0 0010 11rr rrrr
02rr
AND R,A
Z
0 0011 00rr rrrr
03rr
XOR A,R
Z
0 0011 01rr rrrr
03rr
XOR R,A
Z
0 0011 10rr rrrr
03rr
ADD A,R
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
Z
0 0100 01rr rrrr
04rr
MOV R,R
Z
0 0100 10rr rrrr
04rr
COMA R
Z
0 0100 11rr rrrr
04rr
COM R
/R ( R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 ( A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 ( R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 ( A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 ( R, skip if zero
None
0 0110 00rr rrrr
06rr
RRCA R
R(n) ( A(n-1),
R(0) ( C, C ( A(7)
C
1
This instruction is applicable to IOC5 ~ IOC9, IOCA, IOCB, IOCC, IOCD, IOCE, & IOCF only.
2
Source and destination must be the same.