參數(shù)資料
型號: EM73461
廠商: ELAN Microelctronics Corp .
英文描述: Single Chip CMOS 4-Bit Micro-Controller for LCD Product(用于LCD顯示的工作電壓1.2V-1.8V和2.4V-3.6V的單片4位微控制器)
中文描述: 單芯片的CMOS 4位微控制器的LCD產(chǎn)品(用于液晶顯示的工作電壓為1.2V - 1.8V的和為2.4V至3.6V的單片4位微控制器)
文件頁數(shù): 18/34頁
文件大?。?/td> 197K
代理商: EM73461
18
* This specification are subject to be changed without notice.
EM73461
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
7.1.1998
** F
=[(XIN/2
X
)/(100H-HT)]/2, HT=0~255
** Example : LXIN=32K Hz, HIPS=01, HT=11110000B=0F0H.
F
HTC
=[(32K Hz/2
2
)/(100H-0f0H)]/2=256 Hz.
LDIA
#1111B
OUTA
P11
LDIA
#0000B
OUTA
P10
LDIA
#1001B
OUTA
P31
The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into
the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the
next overflow occurs, the preset value can be changed.
The preset value will be changed when users output the different data to P10 and P11.
The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during
counting. Thus, user must disable the counter before reading the value.
The P4.0/SOUND and SOUND pins will output the squre wave in the melody mode. When the CPU is not
in the melody mode, the P4.0/SOUND is high and SOUND is low.
The P4.1/RGH pin will be the input pin in the pulse width measurement mode. User must output high to P4.1/
TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4.1 pin is a normal I/
O pin.
INTERRUPT FUNCTION
There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources . Multiple
interrupts are admitted according the priority .
Type
Interrupt source
Priority
Interrupt
Latch
Interrupt
Enable condition
Program ROM
entry address
External External interrupt(INT0)
Internal
High speed timer overflow interrupt (HTCI)
Internal
TimerA overflow interrupt (TRGA)
Internal
TimerB overflow interrupt (TRGB)
Internal
Time base interrupt(TBI)
External External interrupt(INT1)
1
2
3
4
5
6
IL5 EI=1
IL4
IL3
IL2
IL1
IL0
002H
004H
006H
008H
00AH
EI=1, MASK3=1
EI=1, MASK2=1
EI=1, MASK1=1
EI=1,MASK0=1 00CH
INTERRUPT STRUCTURE
Reset by system reset and program
instruction
MASK0 MASK1 MASK1 MASK2 MASK3
INT1
r0
r1
r2
IL0
IL1
TBI
IL2
IL3
TRGA
r3
IL4
r4
IL5
INT0
r5
Priority checker
EI
Entry address generator
Interrupt request
Interrupt entry address
Reset by system reset and program
instruction
Set by program instruction
TRGB
HTCI
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