參數(shù)資料
型號(hào): EM6640SO18A
英文描述: Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC
中文描述: 微控制器
文件頁(yè)數(shù): 17/62頁(yè)
文件大?。?/td> 620K
代理商: EM6640SO18A
EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
24
www.emmicroelectronic.com
7. 10-bit Counter
The EM6640 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits are
selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.
The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them
are prescaler frequencies and two of these clocks are coming from the input pads PA[0] and PA[3]. In this case
the counter can be used as an event counter.
The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in up
count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter value
matched the compare data register value. Each of this interrupt requests can be masked (default). See section 10
for more information about the interrupt handling.
A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This
data register (Creg[9:0]) is also used to compare its value against Count[9:0] for equivalence.
A Pulse-Width-Modulation signal can be generated and output on PortB PB[3].
7.1 Full, Limited Bit Counting
In Full Bit Counting Mode the counter uses its maximum
of 10-bits length (default ). With the BitSel[1,0] bits in
register RegCDataH one can lower the counter length,
for IRQ generation, to 8, 6 or 4 bits. This means that
actually the counter always uses all the 10-bits, but
IRQCount0 generation is only performed on the number
of selected bits. The unused counter bits may or may not
be taken into account for the IRQComp generation depending on bit SelIntComp. Refer to chapter 7.4.
En
Comparator
ck
Up/Down
Up/Down Counter
En
EvCount
Counter Read Register
RegCDataL, M, H
(Count[9:0])
RegCDataL, M, H (CReg[9:0])
Load
IRQCntComp
PW M
IRQCount0
Data Register
DB[3:0]
PA[0]
ck[19]
ck[16]
ck[13]
ck[10]
ck[4]
ck[1]
PA[3]
ck
MUX
RegCCntl1, 2
CountFSel[2...0]
Up/Down
Start
EvCount
Load
EnComp
Figure 17. 10-bit Counter Block Diagram
Table 6.7—1. Counter length selection
BitSel[1]
BitSel[0 ]
counter length
0
10-Bit
01
8-Bit
10
6-Bit
11
4-Bit
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