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參數資料
| 型號： | EM6605TP24A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-SOIC T&R |
| 中文描述： | 微控制器 |
| 文件頁數： | 34/39頁 |
| 文件大?。?/td> | 675K |
| 代理商： | EM6605TP24A |
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EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
Table 1. Pin Description
Pin Number Pin Name
Function
Remarks
1
port A, 0
input 0 port A
interrupt request; tvar 1
2
port A, 1
input 1 port A
interrupt request; tvar 2
3
port A, 2
input 2 port A
interrupt request; tvar 3
4
port A, 3
input 3 port A
interrupt request; event counter input
5
port B, 0
input / output 0 port B
buzzer output
6
port B, 1
input / output 1 port B
7
port B, 2
input / output 2 port B
8
port B, 3
input / output 3 port B
9
test
test input terminal
for EM test purpose only (internal pull-down)
10
Qout/osc 1
crystal terminal 1
11
Qin/osc 2
crystal terminal 2 (input)
Can accept trimming capacitor tw. Vss
12
Vss
negative power supply terminal
13
STB/RST
strobe / reset status
C reset state + port B, C, D write
14
port C, 0
input / output 0 port C
interrupt request
15
port C, 1
input / output 1 port C
interrupt request
16
port C, 2
input / output 2 port C
interrupt request
17
port C, 3
input / output 3 port C
interrupt request
18
port D, 0
input / output 0 port D
SWB Serial Clock Output
19
port D, 1
input / output 1 port D
SWB Serial Data Output
20
port D, 2
input / output 2 port D
21
port D, 3
input / output 3 port D
22
reset
reset terminal
Active high (internal pull-down)
23
Vreg
internal voltage regulator
Needs typ. 100nF capacitor tw. Vss
24
Vdd
positive power supply terminal
Figure 3.Typical Configuration
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration shown in Fig.3 should be used.
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