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| 型號(hào)： | EM6605DL24A |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 675K |
| 代理商： | EM6605DL24A |
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EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
20
www.emmicroelectronic.com
10 Supply Voltage Level Detector (SVLD)
The EM6603 has a software configurable built-in supply voltage level detector. Three levels can be defined
between VDDmin + 100mV and VDDmax - 600mV in steps of 100mV. During SLEEP mode this function is
disabled.
The required voltage compare level is selected by writing the bits VLC1 and VLC2 in the SVLD control register
which also activates the compare measurement. Since the measurement is not immediate the busy flag
remains high during the measurement and is automatically cleared low when the measurement is finished. The
result is indicated by inspection of the VLDR flag. If the result is 0 then the voltage level is higher than the
selected compare level. And if 1 is lower than the compare level. The result VLDR of the last measurement
remains until the new one is finished. The new result overwrites the previous one.
Table 32. SVLD level selection
During the SVLD operation power consumption increases
by approximately 3
A for 3.9msec. The measurement
internally starts with the rising 256Hz edge following the
SVLD test command. The additional SVLD consumption
stops after the falling edge of the 256Hz internal clock.
Table 32 lists the possible voltage levels
10.1 SVLD register
Table 33.SVLD control register - SVLD
Bit
Name
Reset
R/W
Description
3
VLDR
0
R
SVLD result (0=higher 1=lower)
2
busy
0
R
measurement in progress
1
VLC1
0
R/W
SVLD level control 1
0
VLC0
0
R/W
SVLD level control 0
Evaluation voltage
VLC1
VLC0
not active
0
VL1 (low level)
0
1
VL2
1
0
VL3 (high level)
1
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