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參數(shù)資料
| 型號(hào)： | EM6603SO24B |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 675K |
| 代理商： | EM6603SO24B |
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EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
10
www.emmicroelectronic.com
Debounced PA0 is connected to CPU TestVar1
Debounced PA1 is connected to CPU TestVar2
Debounced PA2 is connected to CPU TestVar3
Figure 6.Port A
Additionally, PA3 can also be used as the input terminal for the event counter (see section 8).
The input port PA(0:3) also has individually selectable interrupts. Each port has its own interrupt mask bit in the
MPortA register. When an interrupt occurs inspection of the IRQpA and the IntRq registers allows the source
of the interrupt to be identified. The IRQpA register is automatically cleared by a RESET, by reading the
register. Reading IRQpA register also clears the INTPA flag in IntRq register. At initial RESET the MPortA is
set to 0, thus disabling any input interrupts.
See also section 9 for further details about the interrupt controller.
6.2 PortA registers
Table 11.PortA input status register - PortA
Bit
Name
Reset
R/W
Description
3
PA3
-
R
PA3 input status
2
PA2
-
R
PA2 input status
1
PA1
-
R
PA1 input status
0
PA0
-
R
PA0 input status
Table 12.PortA Interrupt request register - IRQpA
Bit
Name
Reset
R/W
Description
3
IRQpa3
0
R
input PA3 interrupt request flag
2
IRQpa2
0
R
input PA2 interrupt request flag
1
IRQpa1
0
R
input PA1 interrupt request flag
0
IRQpa0
0
R
input PA0 interrupt request flag
Table 13.PortA interrupt mask register - MportA
Bit
Name
Reset
R/W
Description
3
MPA3
0
R/W
interrupt mask for input PA3
2
MPA2
0
R/W
interrupt mask for input PA2
1
MPA1
0
R/W
interrupt mask for input PA1
0
MPA0
0
R/W
interrupt mask for input PA0
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