
65 COM/ 132SEG Dot Matrix LCD Driver
5
EM65565A
(Continuous)
Pin Name
I/O
Function
# of
Pins
D7 to D0
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus. When the chip select is inactive, D0 to D7 are set
to high impedance.
When the serial interface is selected (P/S = “L”), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
8
Determines whether the data bits are data or the instruction (command).
D/I
D0 to D7
H
Display data
L
Instruction (Command)
D/I
I
1
/RST
I
When /RST is set to “L,” the settings are initialized.
1
/CS1
CS2
I
This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the
chip select CS2 becomes active, and data/command I/O is enabled.
2
/RD
(E)
I
Enable clock signal input for the 68-series MPU, active high.
Active low input pin for the 80-series MPU /RD signal
1
/WR
(R/W)
I
Read/Write control signal with 68-series MPU
R/W=”H”: Read, R/W=”L”: Write
Active low input pin for the 80-series MPU /WR signal
1
MPUS
I
This is the MPU interface switch terminal.
MPUS =”H”: 68-series MPU interface.
MPUS =”L”: 80-series MPU interface.
1
Selects the Parallel or Serial data input interface
P/S = “H”: Parallel data input interface
P/S = “L”: Serial data input interface
The following applies depending on the P/S status:
P/S
Data/Command
Data
Read/Write
Serial Clock
H
D/I
D0 to D7
/RD, /WR
L
D/I
D7 (SI)
Write only
D6 (SCL)
P/S
I
When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open.
RD (E) and WR (P/W) are fixed to either “H” or “L”.
With serial data input, RAM display data reading is not supported.
1
DCLKS
I
Terminal to select whether or enable or disable the display clock internal
oscillator circuit.
DCLKS = “H”: Internal oscillator circuit is enabled
DCLKS = “L”: Internal oscillator circuit is disabled (requires external input)
When DCLKS = “L”, input the display clock through the DCLK terminal.
1