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參數(shù)資料
| 型號(hào)： | EM65565A |
| 英文描述： | Synchronous Rectified MOSFET Driver; Temperature Range: 0°C to 70°C; Package: 8-SOIC |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動(dòng)器，內(nèi)置內(nèi)存 |
| 文件頁(yè)數(shù)： | 33/43頁(yè) |
| 文件大?。?/td> | 291K |
| 代理商： | EM65565A |
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65 COM/ 132SEG Dot Matrix LCD Driver
39
EM65565A
System Bus Read/Write Characteristics 2 (68-Series MPU)
TAW68
TAH68
TEWHR,TEWHW
TCYC68
TEWLR,TEWLW
TDS68
TDH68
TACC68
TOH68
D/I
R/W
/CS1
CS2="1"
E
D0~D7
(write)
D0~D7
(read)
Fig. 16
Table 14
(VDD=2.4V to 3.3V,Ta=-40 to 85°C)
Rating
Item
Signal
Symbol
Condition
Min
Max
Units
Address hold time
Address setup time
D/I
TAH68
TAW68
0
--
ns
System cycle time
D/I
TCYC68
300
--
ns
Data setup time
Data hold time
TDS68
TDH68
40
15
--
ns
Access time
Output disable time
D0 to D7
TACC68
TOH68
CL=100pF
--
10
140
100
ns
Enable H pulse
time
Read
Write
E
TEWHR
TEWHW
120
60
--
ns
Enable L pulse
time
Read
Write
E
TEWLR
TEWLW
60
--
ns
Notes:
1.
The input signal rise time and fall time (TR, TF) is specified at 15 ns or less. When the system cycle
time is extremely fast, (TR+TF) ≦ (TCYC68-TEWLW-TEWHW) for (TR+TF) ≦ (TCYC6-TEWLR-TEWHR) are
specified.
2.
All timing is specified using 20% and 80% of VDD as the reference.
3.
TEWLW and TEWLR are specified as the overlap between /CS1 being “L” (CS2=”H”) and E.
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