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參數(shù)資料
| 型號： | EM65240 |
| 英文描述： | Graphic STN LCD Drivers |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 451K |
| 代理商： | EM65240 |
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EM65240
240 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
4.8.2002
10
FUNCTIONAL DESCRIPTIONS
. Active Control
In case of segment mode, controls the selection or deselection of the chip. Following a LP
signal, and after the chip select signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been completed, a select signal for cascade
connection is output, and the chip is non-selected. In case of common mode, controls the
input/output data of bi-directional pins.
. SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into
latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch circuit,
after that they are put on the internal data bus 8 bits at a time.
. Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus signals.
The shift direction is controlled by the control logic, for every 16 bits of data read in, the
selection signal shifts one bit based on the state of the control circuit.
. Data Latch
In case of segment mode, latches the data on the data bus. The latched state of each LCD
driver output pin is controlled by the control logic and the data latch control, 240 bits of data are
read in 30 sets of 8 bits.
. Line Latch / Shift Register
In case of segment mode, all 240 bits, which have been read into the data latch are
simultaneously latched on the falling edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP signal.
. Level Shifter
The logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver
block.
. 4-level Driver
Drive the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels
(V0, V12, V43, V5) based on the S/C, FR and /DSPOF
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