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參數(shù)資料
| 型號(hào)： | EM65160 |
| 英文描述： | Synchronous Rectified MOSFET Driver; Temperature Range: -40°C to 85°C; Package: 8-QFN |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動(dòng) |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 726K |
| 代理商： | EM65160 |
EM65160
160 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
6/27/2002 (V1.1)
13
Common mode
Table-9 DC Characteristics Of Common Mode
(VSS = 0V, VDD = +2.5 to 5.5V, V0 = +15 to +42V, Ta = -20~85°C)
Parameter
Symbol
Conditions
Applicable pins
Min.
Typ.
Max.
Unit
VIH
0.8VDD
V
Input voltage
VIL
DI0 -DI7, XCK, LP, DIR, FR, MD,
S/C, EIO1, EIO2, /DSPOF
0.2VDD
V
VOH
IOH= -0.4mA
VDD-0.4
V
Output voltage
VOL
IOL= +0.4mA
EIO1, EIO2
+0.4
V
ILIH
VI=VDD
+10
μA
Input leakage current
ILIL
VI=VSS
DI0 -DI7, XCK, LP, DIR, FR, MD,
S/C, EIO1, EIO2, /DSPOF
-10
μA
V0=+40V
0.7
1.0
V0=+30V
1.0
1.5
Output resistance
RON
|ΔVON| =0.5V
V0=+20V
Y1- Y160
1.5
2.0
kΩ
Input pull-down
current
IPD
VI=VDD
XCK, EIO1, EIO2
100.0
μA
Stand-by current
ISTB
*1
VSS
50.0
μA
Consumed current (1)
IDD
*2
VDD
80.0
μA
Consumed current (2)
I0
*2
V0
160.0
μA
NOTE:
1. VDD = +5V, V0 = +42V, VI = VSS
2. VDD = +5V, V0 = +42V, fLP = 41.6kHz, fFR = 80Hz, case of 1/480 duty operation, No-load
AC Electrical characteristic
Segment mode 1
Table-10 AC Electrical Characteristics Of Segment Mode 1
(VSS = 0V, VDD = +4.5 to +5.5V, V0 = +15 to +42V, Ta = -20~85°C)
Parameter
Symbol
Condition
Min.
Type
Max.
Unit
Shift clock period
*1
TWCK
TR,TF≦10ns
71
ns
Shift clock “H” pulse width
TWCKH
23
ns
Shift clock “L” pulse width
TWCKL
23
ns
Data setup time
TDS
10
ns
Data hold time
TDH
20
ns
Latch pulse “H” pulse width
TWLPH
23
ns
Shift clock rise to latch pulse rise time
TLD
0
ns
Shift clock fall to latch pulse fall time
TSL
25
ns
Latch pulse rise to shift clock rise time
TLS
25
ns
Latch pulse fall to shift clock fall time
TLH
25
ns
Input signal rise time *2
TR
50
ns
Input signal fall time
*2
TF
50
ns
Enable setup time
TS
21
ns
/DSPOF removal time
TSD
100
ns
/DSPOF “L” pulse time
TWDL
1.2
μs
Output delay time (1)
TD
CL=15pF
40
ns
Output delay time (2)
TPD1, TPD2
CL=15pF
1.2
μs
Output delay time (3)
TPD3
CL=15pF
1.2
μs
NOTES:
1. Take the cascade connection into consideration.
2. (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high-speed operation.
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