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參數(shù)資料
| 型號： | EM4095HMSO16A |
| 元件分類： | 線性穩(wěn)壓 |
| 英文描述： | Single 12V Input Supply Dual Regulator - Synchronous Rectified Buck PWM and Linear Power Controller; Temperature Range: 0°C to 70°C; Package: 14-SOIC |
| 中文描述： | 電信提供商/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 204K |
| 代理商： | EM4095HMSO16A |
EM4095
Copyright
2002, EM Microelectronic-Marin SA
8
www.emmicroelectronic.com
Read Only mode with external peak detector
P
+5V
L
A
C
DV1
C
DV2
C
RES
P4095
2
3
4
5
6
7
8
1
15
14
13
12
11
10
9
16
+5V
RDY/CLK
D1
R1
C1
C
DEC
C
AGND
MOD
DEMOD_OUT
SHD
C
DC2
C
FCAP
Fig. 10
Read/Write mode with external peak detector
P
+5V
L
A
C
DV1
C
DV2
C
RES
C
DEC
P4095
2
3
4
5
6
7
8
1
15
14
13
12
11
10
9
16
+5V
RDY/CLK
D1
R1
C1
C
AGND
MOD
DEMOD_OUT
SHD
C
DC2
C
FCAP
Fig. 11
As mentioned above for high Q antennas the voltage on
antenna is high and read sensitivity is limited by
demodulator sensitivity due to capacitive divider. Read
sensitivity (and thus reading range) can be increased by
using external envelope detector circuit. Input is taken on
antenna high voltage side output is directly fed to
CDEC_IN pin. However, the capacitor divider is still
needed for PLL locking. Such configuration is shown in
figure 5, the envelope detector is formed by three
components: D1, R1 and C1.
The configuration presented in figure 9 may also be used
for read write applications but it has a drawback in the
case
fast
recovery
of
reading
is
needed
after
communication reader to transponder is finished. The
reason is in fact that DC voltage after diode D1 is lost
during modulation and it takes very long time before it is
established again.
Figure 10 presents a solution to that problem. A high
voltage NMOS transistor blocks the discharge path during
modulation, so operating point is preserved. The signal
controlling NMOS gate has to be put low synchronously
with signal MOD, but it can be put high only after the
amplitude on antenna has recovered after modulation.
PCB Layout
Refer to "EM4095 Application Note" (App. Note 404)
EM4095
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