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參數(shù)資料
| 型號： | EM4069B6CI2LC |
| 英文描述： | Analog Miscellaneous |
| 中文描述： | 模擬雜項 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 169K |
| 代理商： | EM4069B6CI2LC |
EM4069
EM4169
Copyright
2002, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Timing Characteristics
VDD = 3.0 V, VSS = 0 V, fCOIL1 = 125 kHz square wave, VCOIL1 = 5V, TOP = 25°C, unless otherwise specified
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Option : 64 RF periods per bit
Read bit period
tRDB
64
RF periods
EEPROM write time
tWee
20
ms
Synchronization pattern phase 1
tS1
4.1
5.0
ms
Synchronization pattern phase 2
tS2
1.5
2.0
ms
Synchronization pattern phase 3
tS3
1.5
4.0
ms
Option : 32 RF periods per bit
Read bit period
tRDB
32
RF periods
EEPROM write time
tWee
20
ms
Synchronization pattern phase 1
tS1
2.1
2.5
ms
Synchronization pattern phase 2
tS2
0.8
1.0
ms
Synchronization pattern phase 3
tS3
0.8
2.0
ms
RF periods represent periods of the carrier frequency emitted by the transceiver unit.
See figure 12 for Synchronization pattern phases.
Due to amplitude modulation of the coil-signal, the clock-extractor may miss clocks or add spurious clocks close to
the edges of the RF-envelope. This desynchronization will not be larger than
±±±± 3 clocks per bit and must be taken into
account when developing reader software.
Block Diagram
Modulator
Control
Logic
EEPROM
Clock
Extractor
Sequencer
Data
Extractor
CR
Cbuf
VDD
VSS
Power
Supply
Reset
Power on
Reset
COIL1
VSS
ROM
Fig. 3
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