參數(shù)資料
型號(hào)： ELANSC410-66AC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝： PLASTIC, BGA-292
文件頁數(shù)： 20/132頁
文件大?。?/td> 2400K
代理商： ELANSC410-66AC
20
élanSC400 and élanSC410 Microcontrollers Data Sheet
ISA Bus Interface For External ISA Peripherals
The ISA interface consists of a subset of ISA-compati-
ble bus signals, allowing for the connection of 8- or
16-bit devices supporting ISA-compatible I/O, memory,
and DMA cycles. The following features are supported:
I
8.2944-MHz maximum bus clock speed
I
Programmable DMA clock speed up to 16 MHz
I
8-bit and 16-bit ISA I/O and memory cycles (ISA
memory is non-cacheable)
I
Direct connection to 3- or 5-volt peripherals
Eight programmable IRQ input signals are available.
These interrupts can be routed via software to any
available PC/AT-compatible interrupt channel.
Two programmable DMA channels are available for ex-
ternal DMA peripherals. These DMA channels can be
routed to software to any available ISA DMA channel.
VESA Local (VL) Bus Interface Supports 32-Bit
Memory and I/O Targets
The VESA local (VL) bus controller provides the sig-
nals and associated timing necessary to support a sin-
gle VESA compliant VL-bus target. Multiple VL-bus
targets can be supported using external circuitry to
allow multiple VL devices to share the VL_LDEV sig-
nal. This allows the élanSC400 and élanSC410 micro-
controllers to operate as a normal VL-bus motherboard
controller, in accordance with the
VL-Bus Standard 2.0
.
On the élanSC400 microcontroller, the VL-bus is
available only when the internal graphics controller is
disabled.
The microcontroller’s VL-bus controller includes the
following features:
I
33-MHz operation at 3.3 V
I
32-bit data bus
I
Burst-mode transfers
I
Register control of local bus reset
VESA bus mastering and DMA transfers to and from
the VL-bus target are not supported. VL memory is
non-cacheable.
SYSTEM CONSIDERATIONS
Figure 1 shows the élanSC400 microcontroller as it
might be used in a minimal system design.
Figure 2 and Figure 3 show more complex system de-
signs for each microcontroller and the features that are
traded for others because of pin multiplexing.
I
The élanSC400 and élanSC410 microcontrollers
support a maximum of 4 banks of 32-bit DRAM, but
because the RAS and CAS signals for the high
word and for banks 2 and 3 are traded for keyboard
row signals, the minimum system would have one
or two banks of DRAM (either Bank 0 or Bank 1)
populated with 16-bit DRAMs. The MA12 signal for
asymmetrical support is also traded with a keyboard
row signal.
I
Because the VL-bus and the graphics controller
share control signals on the élanSC400 microcon-
troller, use of the internal graphics controller is
traded with having an external VL-bus on that mi-
crocontroller.
I
If either 32-bit DRAMs, 32-bit ROMs, or the VL-bus
is enabled, the internal graphics controller on the
élanSC400 microcontroller is unavailable because
of internal design constraints.
I
The élanSC400 and élanSC410 microcontrollers
provide an absolute minimum of dedicated ISA con-
trol signals. Any additional ISA controls are traded
with GPIOs or keyboard rows and columns.
I
The SD buffer shares control signals with some of
the GPIOs. This buffer controls the high word of the
D data bus (D31–D16). Note that using the SD
buffer is optional. The high word of the D data bus
can be hooked up directly to devices that want the
SD data bus (SD15–SD0). Buffering aids in voltage
translation or isolation for heavy loading.
I
The R32BFOE signal buffers the high word of the D
data bus (D31–D16) for 32-bit ROMs. The control
signal associated with the ROM32 buffer is shared
with a keyboard row.
I
On the élanSC400 microcontroller, the parallel port
is traded for PC Card Socket B. It requires an exter-
nal buffer and latch.
I
The serial and infrared ports share the same inter-
nal UART. Real-time switching between the two is
supported; however, only one port is available at
any given time.
I
ROMCS2 is not connected to a dedicated pin. Soft-
ware can enable and map it to any of the 15
GPIO_CS signals.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ELANSC410-66ACAD 制造商:Advanced Micro Devices 功能描述:
ELANSC410-66AI 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA
ELANSC520 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Microcontroller
ELANSC520100AC 制造商:Advanced Micro Devices 功能描述:
ELANSC520-100AC 制造商:Advanced Micro Devices 功能描述:MCU 32-bit Elan RISC ROMLess 388-Pin BGA 制造商:Advanced Micro Devices 功能描述:PLASTIC BGA, CAVITY UP(BGA) - Trays 制造商:AMD (Advanced Micro Devices) 功能描述:MCU 32-bit Elan RISC ROMLess 388-Pin BGA
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