參數(shù)資料
型號： ELANSC410-100AI
廠商： Advanced Micro Devices, Inc.
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 單芯片，低功耗的PC / AT兼容微控制器
文件頁數(shù)： 65/132頁
文件大?。?/td> 2400K
代理商： ELANSC410-100AI
élanSC400 and élanSC410 Microcontrollers Data Sheet
65
VL_BRDY
I
Local Bus Burst Ready
is asserted by the VL-bus target to indicate that it is terminating the
current burst transfer. The chip samples this signal on the rising edge of VL_LCLK.
VL_BRDY should be asserted for one VL_LCLK period per burst transfer. If VL_LRDY is
asserted at the same time as VL_BRDY, VL_BRDY is ignored and the VL-bus transfer is
terminated.
Local Bus Data/Code Status
is driven Low to indicate that code is being transferred. A High
on this signal indicates that data is being transferred.
Local Bus Memory/I/O Status
is driven Low to indicate an I/O transfer. A High on this signal
indicates a memory transfer.
Local Bus Write/Read Status
is driven Low to indicate a read transfer. A High on this signal
indicates a write.
VL_D/C
VL_M/IO
VL_W/R
O
O
O
VL_LCLK
O
Local Bus Clock
is the VL-bus clock. It is used by the VL-bus target for all timing references.
This signal is in phase with the internal CPU’s clock input.
(Rising Edge Active)
Local Bus Device Select
is asserted by the VL-bus target to indicate that it is accepting the
current transfer as indicated by the address and status lines. The VL-bus target asserts this
signal as a function of the address and status presented on the bus.
Local Bus Ready
is asserted by the VL-bus target to indicate that it is terminating the current
bus cycle. This signal is sampled by the chip on the rising edge of VL_LCLK.
Local Bus Reset
is the VL-bus master reset. It is controlled with CSC index 14h[4].
VL_LDEV
I
VL_LRDY
I
VL_RST
Power Management
ACIN
O
I
AC Supply Active
indicates to the system that it is being powered from an AC source. When
asserted, this signal can disable power management functions (if configured to do so).
Battery Low Detects
indicate to the chip the current status of the system’s primary battery
pack. BL0–BL2 can indicate various conditions of the battery as conditions change. These
inputs can be used to force the system into one of the power saving modes when activated
(Low-going Edge).
Latched Battery Low Detect 2
can be driven Low and latched on the low-going edge of the
BL2 input to indicate to the system that the chip has been forced into the Suspend mode by
a battery dead indication from the BL2 signal. It is cleared by one of the “all clear” indicators
that allow the system to resume after a battery dead indication.
Suspend/Resume Operation:
When the chip is in Hyper-Speed, High-Speed, Low-Speed,
or Standby mode, a software-configurable edge on this pin can cause the internal logic to
enter Suspend mode. When in Suspend, a software-configurable edge on this pin can cause
the chip to enter the High-Speed or Low-Speed mode. The choice of edge is configured using
the SUS_RES Pin Configuration Register at CSC index 50h.
BL2–BL0
I
LBL2
O
SUS_RES
I
Table 19.
Signal Description Table (Continued)
Signal
Type
Description
Bus Cycle Initiated
Interrupt Acknowledge
Halt/Special Cycle
I/O Read
I/O Write
Code Read
Reserved
Memory Read
Memory Write
VL_M/IO
0
0
0
0
1
1
1
1
VL_D/C
0
0
1
1
0
0
1
1
VL_W/R
0
1
0
1
0
1
0
1
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