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參數(shù)資料
| 型號(hào)： | ELANSC410-100AC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| 中文描述： | 32-BIT, FLASH, 100 MHz, MICROCONTROLLER, PBGA292 |
| 封裝： | PLASTIC, BGA-292 |
| 文件頁(yè)數(shù)： | 63/132頁(yè) |
| 文件大?。?/td> | 2400K |
| 代理商： | ELANSC410-100AC |
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élanSC400 and élanSC410 Microcontrollers Data Sheet
63
MEMR
O
Memory Read Command
indicates that the current cycle is a read of the currently
addressed memory device. When this signal is asserted, the memory device can drive data
onto the data bus.
Memory Write Command
indicates that the current cycle is a write of the currently
addressed memory device. When this signal is asserted, the memory device can latch data
from the data bus.
Programmable DMA Acknowledge
signals can each be mapped to one of the seven
available DMA channels. They are driven active (Low) back to the DMA initiator to
acknowledge the corresponding DMA requests.
Programmable DMA Requests
can each be mapped to one of the seven available DMA
channels. They are asserted active (High) by a DMA initiator to request DMA service from
the DMA controller.
Programmable Interrupt Requests
can each be mapped to one of the available 8259
interrupt channels. They are asserted when a peripheral requires interrupt service.
(Rising Edge/Active High Trigger)
System Reset
is the ISA bus reset signal. When this signal is asserted, all connected
devices reinitialize to their reset state. This signal should not be confused with the internal
CPU RESET and SRESET signals.
System Address Bus
outputs the physical memory or I/O port latched addresses. It is used
by all external peripheral devices other than main system DRAM. In addition, this is the local
address bus in local bus mode.
System Byte High Enable
is driven active when the high data byte is to be transferred on
the upper 8 bits of the ISA data bus.
System Data Bus
is shared between ISA, 8- or 16-bit ROM/Flash memory, and PC Card
peripherals (on the élanSC400 microcontroller only) and can be directly connected to all of
these devices. In addition, these signals are the upper word of the local data bus, the 32-bit
DRAM interface, and the 32-bit ROM interface. In these modes, the system data bus can be
generated via an external buffer connected to the SD bus and controlled by the buffer control
signals provided.
Speaker, Digital Audio Output
controls an external speaker driver. It is generated from the
internal 8254-compatible timer Channel 2 output ANDed with I/O Port 0061h[1] (Speaker
Data Enable); on the élanSC400 microcontroller, the PC Card speaker signals are
exclusively ORed with each other and the speaker control function of the timer to generate
the SPKR signal.
Terminal Count
is driven from the DMA controller pair to indicate that the transfer count for
the currently active DMA channel has reached zero, and that the current DMA cycle is the
last transfer.
MEMW
O
PDACK1
–PDACK0
O
PDRQ1–PDRQ0
I
PIRQ7–PIRQ0
I
RSTDRV
O
SA25–SA0
O
SBHE
O
SD15–SD0
B
SPKR
O
TC
O
Configuration Pins
BNDSCN_EN
I
Boundary Scan Enable
enables the boundary scan pin functions. When this pin is High, the
boundary scan interface is enabled. When this pin is Low, the boundary scan pin functions
are disabled and the pins are configured to their default functions. This pin must be held Low
during reset for normal operation.
Configuration Pins 1–0
select the data bus width for the physical device(s) selected by the
ROMCS0 pin (i.e., 8-, 16-, or 32-bit-wide). These pins are sampled at the deassertion of RESET.
Configuration Pin 2
selects whether or not the system will boot from PC Card Socket A
memory card or from the device attached to ROMCS0. This pin is sampled at the deassertion
of RESET
. This pin is not supported on the élanSC410 microcontroller.
Configuration Pin 3
enables the SD buffer control signals, DBUFOE, DBUFRDH, and
DBUFRDL. This pin is sampled at the deassertion of RESET.
CFG1–CFG0
I
CFG2
I
CFG3
I
Table 19.
Signal Description Table (Continued)
Signal
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ELANSC410-100AI | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-33AC | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-33AI | 5566-12BGS /N/MINI FIT CONN HOUS ASSY |
| ELANSC410-66AC | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-66AI | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC410-100ACAD | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC410-100AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-33AC | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC 3.3V 292-Pin BGA |
| ELANSC410-33AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| ELANSC410-66AC | 制造商:Advanced Micro Devices 功能描述:MCU 32-bit Elan RISC ROMLess 3.3V 292-Pin BGA 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC 3.3V 292-Pin BGA 制造商:Advanced Micro Devices 功能描述:Microprocessor, 32 Bit, 292 Pin, Plastic, BGA |
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