參數(shù)資料
型號(hào)： EL9115ILZ-T7
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： Header; No. of Contacts:4; Pitch Spacing:0.165"; No. of Rows:2; Series:Mini-Fit Jr.; Body Material:Nylon 6/6 RoHS Compliant: Yes
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC20
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-20
文件頁(yè)數(shù)： 3/9頁(yè)
文件大小： 581K
代理商： EL9115ILZ-T7
3
FN7441.2
September 8, 2005
AC Electrical Specifications
V
SA
+
= V
A
+
= +5V, V
SA
-
= V
A
-
= -5V, T
A
= 25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
BW -3dB
3 dB Bandwidth
0ns Delay Time
122
MHz
BW 0.1dB
0.1dB Bandwidth
0ns Delay Time
60
MHz
SR
Slew Rate
0ns Delay Time
400
V/μs
T
R
- T
F
Transient Response Time
20% - 80%, for all delays, 1V step
2.5
ns
V
OVER
Voltage Overshoot
for any delay, response to 1V step input
5
10
%
Glitch
Switching Glitch
Time for o/p to settle after last s_clock edge
100
ns
THD
Total Harmonic Distortion
1V
P-P
10MHz sinewave, offset by +0.2V at
mid delay setting
-50
-40
dB
X
T
Hostile Crosstalk
Stimulate G, measure R/B at 1MHz
-80
dB
V
N
Output Noise
Gain X2, measured at 75
load
2.5
mV rms
d
T
Delay Increment
1.75
2
2.25
ns
T
MAX
Maximum Delay
55
62
70
ns
D
ELDT
Delay Diff Between Channels
1.6
%
t
PD
Propagation Delay
Measured input to output
8.5
9.8
11
ns
T
MAX
Max s_clock Frequency
Maximum programming clock speed
10
MHz
T_en_ck
Minimum Separation Between Serial
Enable and Clock .
Check enable low edge can occur after
T_en_ck of previous (igored) clock and up to
before T_en_ck of next (wanted) clock. Clock
edges occurring within T_en_ck of the enable
edge will have ncertain effect.
10
ns
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VSP
+5V for delay circuitry and input amp
2
RIN
Red channel input, ref GND
3
GND
0V for delay circuitry supply
4
GIN
Green channel input, ref GND
5
VSM
-5V for input amp
6
BIN
Blue channel input, ref GND
7
CENABLE
Chip enable logical +5V enables chip
8
NSENABLE
ENABLE for serial input; enable on low
9
SDATA
Data into registers; logic threshold 1.2V
10
SCLOCK
Clock to enter data; logical; data written on negative edge
11
BOUT
Blue channel output, ref GND
O
12
VSMO
-5V for output buffers
13
GOUT
Green channel output, ref GND
O
14
GNDO
0V reference for input and output buffers
15
ROUT
Red channel output, ref GND
O
16
VSPO
+5V for output buffers
17
TESTB
Blue channel phase detector output
18
TESTG
Green channel phase detector output
19
TESTR
Red channel phase detector output
20
X2
Sets gain to 2X if input high; X1 otherwise
Thermal Pad
Must be connected to -5V
EL9115
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