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參數(shù)資料
| 型號(hào)： | EL8101IW-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 200MHZ R-R SOT-23-5 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 200 V/µs |
| 增益帶寬積： | 100MHz |
| -3db帶寬： | 200MHz |
| 電流 - 輸入偏壓： | 1.5µA |
| 電壓 - 輸入偏移： | 800µV |
| 電流 - 電源： | 2mA |
| 電流 - 輸出 / 通道： | 65mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5 V，±1.5 V ~ 2.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
10
FN7103.9
September 14, 2010
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7F tantalum
capacitor in parallel with a 0.1F ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
Video Sync Pulse Remover
Many CMOS analog to digital converters have a parasitic
latch up problem when subjected to negative input voltage
levels. Since the sync tip contains no useful video
information and it is a negative going pulse, we can chop it
off. Figure 27 shows a gain of 2 connections for EL8100,
EL8101. Figure 28 shows the complete input video signal
applied at the input, as well as the output signal with the
negative going sync pulse removed.
Multiplexer
Besides the normal power-down usage, the ENABLE pin of
the EL8100 can be used for multiplexing applications.
Figure 29 shows two EL8100s with the outputs tied together,
driving a back terminated 75
Ω video load. A 2VP-P 2MHz
sine wave is applied to Amp A and a 1VP-P 2MHz sine wave
is applied to Amp B. Figure 30 shows the ENABLE signal
and the resulting output waveform at VOUT. Observe the
break-before-make operation of the multiplexing. Amp A is
on and VIN1 is passed through to the output when the
ENABLE signal is low and turns off in about 25ns when the
ENABLE signal is high. About 200ns later, Amp B turns on
and VIN2 is passed through to the output. The
break-before-make operation ensures that more than one
amplifier isn’t trying to drive the bus at the same time.
FIGURE 27. SYNC PULSE REMOVER
5V
1K
VOUT
VIN
75
Ω
+
-
75
Ω
1k
75
Ω
VS+
VS-
FIGURE 28. VIDEO SIGNAL
1.0V
0.5V
0V
1.0V
0.5V
0V
M = 10s/DIV
VOUT
VIN
FIGURE 29. TWO TO ONE MULTIPLEXER
+2.5V
1k
2MHz
75
Ω
+
-
1K
75
Ω
-2.5V
VOUT
75
Ω
1VP-P
B
+2.5V
1K
2MHz
+
-
1k
75
Ω
-2.5V
2VP-P
A
ENABLE
EL8100, EL8101
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