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參數(shù)資料
| 型號(hào)： | EL7571C |
| 英文描述： | Programmable PWM Controller |
| 中文描述： | 可編程PWM控制器 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 480K |
| 代理商： | EL7571C |
3
EL7571C
Programmable PWM Controller
E
L
75
71
C
AC Electrical Characteristics
TA = 25°C, VIN = 5V, COSC = 330pF, CSLOPE = 390pF unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
Unit
fOSC
Nominal Oscillator Frequency
COSC = 330pF
140
190
240
kHz
fCLK
Clock Frequency
50
500
1000
kHz
tOTEN
Shutdown Delay
VOTEN>1.5V
100
ns
tSYNC
Oscillator Sync. Pulse Width
Oscillator i/p (COSC) driven with HCMOS
gate
20
800
ns
TSTART
Soft-start Period
VOUT = 3.5V
100/fCLK
us
DMAX
Maximum Duty Cycle
97
%
Pin Descriptions
Pin No.
Pin
Name
Pin
Type [1]
Function
1
OTEN
I
Chip enable input, internal pull up (5mA typical). Active high.
2
CSLOPE
I
With a capacitor attached from CSLOPE to GND, generates the voltage ramp compensation for the PWM current mode con-
troller. Slope rate is determined by an internal 14uA pull up and the CSLOPE capacitor value. VCSLOPE is reset to ground at
the termination of the high side cycle.
3
COSC
I
Multi-function pin: with a timing capacitor attached, sets the internal oscillator rate fS (kHz) = 57/COSC (F); when pulsed
low for a duration tSYNC synchronizes device to an external clock.
4
REF
O
Band gap reference output. Decouple to GND with 0.1uF.
5
PWRGD
O
Power good, open drain output. Set low whenever the output voltage is not within ±13% of the programmed value.
6
VID0
I
Bit 0 of the output voltage select DAC. Internal pull up sets input high when not driven.
7
VID1
I
Bit 1 of the output voltage select DAC. Internal pull up sets input high when not driven.
8
VID2
I
Bit 2 of the output voltage select DAC. Internal pull up sets input high when not driven.
9
VID3
I
Bit 3 of the output voltage select DAC. Internal pull up sets input high when not driven.
10
VID4
I
Bit 4 of the output voltage select DAC. Internal pull up sets input high when not driven.
11
FB
I
Voltage regulation feedback input. Tie to VOUT for normal operation.
12
CS
I
Current sense. Current feedback input of PWM controller and over current capacitor input. Current limit threshold set at
+154mV with respect to FB. Connect sense resistor between CS and FB for normal operation.
13
GND
S
Ground
14
GNDP
S
Power ground for low side FET driver. Tie to GND for normal operation.
15
LSD
O
Low side gate drive output.
16
VINP
S
Input supply voltage for low side FET driver. Tie to VIN for normal operation.
17
VIN
S
Input supply voltage for control unit.
18
LX
S
Negative supply input for high side FET driver.
19
HSD
O
High side gate drive output. Driver ground referenced to LX. Driver supply may be bootstrapped to enhance low controller
input voltage operation.
20
VH1
S
Positive supply input for high side FET driver.
1.
Pin designators: I = Input, O = Output, S = Supply
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