參數(shù)資料
型號: EL5421TIYZ-T13
廠商: Intersil
文件頁數(shù): 3/13頁
文件大小: 0K
描述: IC BUFFER R-R 12MHZ 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 緩沖器
電路數(shù): 4
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 12 V/µs
-3db帶寬: 12MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 4000µV
電流 - 電源: 550µA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 19 V,±2.25 V ~ 9.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
11
FN6922.0
September 25, 2009
phase margin and the stability of the EL5421T. The
advantage of a snubber circuit is that it does not draw any
DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1
Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5421T buffers,
it is possible to exceed the +150°C absolute maximum
junction temperature under certain load current conditions. It
is important to calculate the maximum power dissipation of
the EL5421T in the application. Proper load conditions will
ensure that the EL5421T junction temperature stays within a
safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
Θ
JA = Thermal resistance of the package
PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the loads,
or:
when sourcing, and:
when sinking.
Where:
i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
VS = Total supply voltage (VS+ - VS-)
VS+ = Positive supply voltage
VS- = Negative supply voltage
ISMAX = Maximum supply current per buffer
(ISMAX = EL5421T quiescent current ÷ 4)
VOUT = Output voltage
ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in the
highest power dissipation. To find RLOAD set the two PDMAX
equations equal to each other and solve for VOUT/ILOAD.
Reference the package power dissipation curves, Figures 27
and 28, for further information.
P
DMAX
T
JMAX
T
AMAX
Θ
JA
---------------------------------------------
=
(EQ. 1)
P
DMAX
ΣiV
[
S
I
SMAX
V
(
S+VOUT i )
I
LOADi
×
+
×]
=
(EQ. 2)
P
DMAX
ΣiV
[
S
I
SMAX
V
(
OUT iVS- )
I
LOAD i
×
+
×]
=
(EQ. 3)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0
1
2
3
4
5
6
7
8
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
P
O
WER
DIS
S
IPATION
(W)
625mW
MSOP10
θJA = +200°C/W
85
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
25
50
75
100
125
150
POWER
DISS
IP
A
T
ION
(W)
781mW
MSOP10
θJA = +160°C/W
85
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
EL5421T
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