參數(shù)資料
型號(hào): EL5325AIREZ-T7
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: 12-Channel TFT-LCD Reference Voltage Generator with External Shutdown
中文描述: 12-OUTPUT THREE TERM VOLTAGE REFERENCE, PDSO28
封裝: ROHS COMPLIANT, MO-153, HTSSOP-28
文件頁(yè)數(shù): 11/12頁(yè)
文件大?。?/td> 851K
代理商: EL5325AIREZ-T7
8
Block Diagram
Analog Section
TRANSFER FUNCTION
The transfer function is:
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5325A will be derived from
the reference voltages present at the VREFL and VREFH
pins. The impedance between those two pins is about 32k
Ω.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5325A. GND < VREFH ≤ VS and GND ≤ VREFL ≤ VREFH.
In some LCD applications that require more than 12
channels, the system can be designed such that one
EL5325A will provide the Gamma correction voltages that
are more positive than the VCOM potential. The second
EL5325A can provide the Gamma correction voltage more
negative than the VCOM potential. The Application Drawing
shows a system connected in this way.
CLOCK OSCILLATOR
The EL5325A requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling
OSC clock edges. The output refreshed switches open at the
rising edges of the OSC clock. The driving load shouldn’t be
changed at the rising edges of the OSC clock. Otherwise, it
will generate a voltage error at the outputs. This clock may be
input or output via the clock pin labeled OSC. The internal
clock is provided by an internal oscillator running at
approximately 21kHz and can be output to the OSC pin. In a 2
chip system, if the driving loads are stable, one chip may be
programmed to use the internal oscillator; then the OSC pin
will output the clock from the internal oscillator. The second
chip may have the OSC pin connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting B14 to high, the
VOLTAGE
SOURCES
EIGHT
CHANNEL
MEMORY
CONTROL IF
CLK
SDI
EXT_OSC
REFERENCE DECOUPLE
REFERENCE LOW
OUTL
OUTK
OUTJ
OUTB
OUTA
REFERENCE HIGH
FILTER
LOAD
SDO
VOUT IDEAL)
(
VREFL
=
data
1024
-------------
VREFH - VREFL
()
×
+
EL5325A
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