參數(shù)資料
型號(hào): EL5176IY-T13
廠商: INTERSIL CORP
元件分類: 通用總線功能
英文描述: 250MHz Differential Twisted-Pair Driver
中文描述: LINE DRIVER, PDSO8
封裝: MO-187, MSOP-8
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 406K
代理商: EL5176IY-T13
9
FN7343.2
August 3, 2005
in parallel with R
F
can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5176 depends on the load and the
feedback network. R
F
and R
G
appear in parallel with the
load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, R
F
also has a
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, R
F
= 0 is optimum.
For the gains other than +1, optimum response is obtained
with R
F
between 500
to 1k
.
The EL5176 has a gain bandwidth product of 100MHz for
R
LD
= 1k
. For gains
5, its bandwidth can be predicted by
the following equation:
Driving Capacitive Loads and Cables
The EL5176 can drive 50pF differential capacitor in parallel
with 1k
differential load with less than 5dB of peaking at
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5
to 50
) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor R
G
can then be chosen to make up
for any gain loss which may be created by the additional
series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5176 can be disabled and placed its outputs in a high
impedance state. The turn off time is about 0.95μs and the
turn on time is about 215ns. When disabled, the amplifier's
supply current is reduced to 1.7μA for I
S
+ and 120μA for I
S
-
typically, thereby effectively eliminating the power
consumption. The amplifier's power down can be controlled
by standard CMOS signal levels at the ENABLE pin. The
applied logic signal is relative to V
S
+ pin. Letting the EN pin
float or applying a signal that is less than 1.5V below V
S
+ will
enable the amplifier. The amplifier will be disabled when the
signal at EN pin is above V
S
+ - 0.5V.
Output Drive Capability
The EL5176 has internal short circuit protection. Its typical
short circuit current is ±40mA for EL5176. If the output is
shorted indefinitely, the power dissipation could easily
increase such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
±40mA. This limit is set by the design of the internal metal
interconnect.
Power Dissipation
With the high output drive capability of the EL5176. It is
possible to exceed the 135°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
Where:
T
JMAX
= Maximum junction temperature
T
AMAX
= Maximum ambient temperature
θ
JA
= Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
Where:
V
S
= Total supply voltage
I
SMAX
= Maximum quiescent supply current per channel
V
O
= Maximum differential output voltage of the
application
R
LD
= Differential load resistance
I
LOAD
= Load current
By setting the two PD
MAX
equations equal to each other, we
can solve the output current and R
LD
to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V
S
- pin is
connected to the ground plane, a single 4.7μF tantalum
capacitor in parallel with a 0.1μF ceramic capacitor from V
S
+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V
S
- pin becomes the negative
supply rail.
Gain
BW
100MHz
=
×
PD
MAX
T
--------------------------------------------
T
JA
=
PD
V
S
I
SMAX
V
S
V
O
LD
-----------
×
+
×
=
EL5176
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