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參數(shù)資料
| 型號： | EL4585CSZ-T7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | Horizontal Genlock, 8FSC |
| 中文描述： | 36 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SO-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 262K |
| 代理商： | EL4585CSZ-T7 |
EL4585C
Horizontal Genlock 8 FSC
AC Electrical Characteristics (V
DD
e
5V TAe25 C unless otherwise noted)
Parameter
Conditions
Temp
Min
Typ
Max
Test
Units
Level
VCO Gain
20 MHz
Test circuit 1
25 C
155
V
dB
H-sync SN Ratio
VDDe5V (Note 2)
25 C35
V
dB
Jitter
VCXO Oscillator
25 C1
V
ns
Jitter
LC Oscillator (Typ)
25 C10
V
ns
Note 2 Noisy video signal input to EL4583C H-sync input to EL4585C Test for positive signal lock
Pin Description
Pin No
Pin Name
Function
16 1 2
Prog ABC
Digital inputs to select d N value for internal counter See table below for values
3
OscVCO Out
Output of internal inverteroscillator Connect to external crystal or LC tank VCO circuit
4VDD (A)
Analog positive supply for oscillator PLL circuits
5
OscVCO In
Input from external VCO
6VSS (A)
Analog ground for oscillator PLL circuits
7
Charge Pump
Connect to loop filter If the H-sync phase is leading or H-sync frequency l CLKd2N current is
pumped into the filter capacitor to increase VCO frequency If H-sync phase is lagging or frequency
Out
k
CLKd2N current is pumped out of the filter capacitor to decrease VCO frequency During coast
mode or when locked charge pump goes to a high impedance state
8
Div Select
Divide select input When high the internal divider is enabled and EXT DIV becomes a test pin
outputting CLKd2N When low the internal divider is disabled and EXT DIV is an input from an
external dN
9
Coast
Tri-state logic input Low(k
VCC) e normal mode Hi Z(or
to
VCC) e fast lock mode
High(l
VCC) e coast mode
10
H-sync In
Horizontal sync pulse (CMOS level) input
11
VDD (D)
Positive supply for digital IO circuits
12
Lock Det
Lock Detect output Low level when PLL is locked Pulses high when out of lock
13
Ext Div
External Divide input when DIV SEL is low internal d 2N output when DIV SEL is high
14
VSS (D)
Ground for digital IO circuits
15
CLK Out
Buffered output of the VCO
Table 5 VCO Divisors
Prog A
Prog B
Prog C
Div Value
Pin 16
Pin 1
Pin 2
N
0
1702
0
1
1728
0
1
0
1888
0
1
2270
1
0
1364
1
0
1
1716
1
0
1560
1
1820
3
TD
is
35in
TD
is
35in
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