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    參數(shù)資料
    型號: EL4585CS
    英文描述: Horizontal Genlock, 8 FSC
    中文描述: 水平同步鎖相,8金管會
    文件頁數(shù): 1/16頁
    文件大?。?/td> 262K
    代理商: EL4585CS
    EL4585C
    March
    1996
    Rev
    C
    EL4585C
    Horizontal Genlock 8 FSC
    Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
    specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
    4585C
    1995 Elantec Inc
    Features
    36 MHz general purpose PLL
    8FSC timing (Use the EL4584
    for4FSC)
    Compatible with EL4583C Sync
    Separator
    VCXO Xtal or LC tank
    oscillator
    k2nS jitter (VCXO)
    User-controlled PLL capture and
    lock
    Compatible with NTSC and PAL
    TV formats
    8 pre-programmed popular TV
    scan rate clock divisors
    Single 5V low current operation
    Applications
    Pixel Clock regeneration
    Video compression engine
    (MPEG) clock generator
    Video Capture or digitization
    PIP (Picture In Picture) timing
    generator
    Text or Graphics overlay timing
    Ordering Information
    Part No
    Temp Range
    Package
    Outline
    EL4585CN
    b
    40 Cto a85 C 16-Pin DIP
    MDP0031
    EL4585CS
    b
    40 Cto a85 C 16-Lead SO
    MDP0027
    For 3Fsc and 4Fsc clock frequency operation
    see EL4584 datasheet
    Demo Board
    A demo PCB is available for this
    product Request ‘‘EL45845 Demo
    Board’’
    General Description
    The EL4585C is a PLL (Phase Lock Loop) sub system designed
    for video applications but also suitable for general purpose use
    up to 36 MHz In a video application this device generates a
    TTLCMOS compatible Pixel Clock (Clk Out) which is a multi-
    ple of the TV Horizontal scan rate and phase locked to it
    The reference signal is a horizontal sync signal TTLCMOS
    format which can be easily derived from an analog composite
    video signal with the EL4583 Sync Separator An input signal
    to ‘‘coast’’ is provided for applications where periodic distur-
    bances are present in the reference video timing such as VTR
    head switching The Lock detector output indicates correct lock
    The divider ratio is four ratios for NTSC and four similar ratios
    for the PAL video timing standards by external selection of
    three control pins These four ratios have been selected for com-
    mon video applications including 8 FSC 6FSC 27 MHz (CCIR
    601 format) and square picture elements used in some worksta-
    tion graphics To generate 4 FSC 3FSC 135 MHz (CCIR 601
    format) etc use the EL4584 which does not have the addition-
    al divide by 2 stage of the EL4585
    For applications where these frequencies are inappropriate or
    for general purpose PLL applications the internal divider can be
    by passed and an external divider chain used
    FREQUENCIES and DIVISORS
    Function
    6Fsc
    CCIR 601
    Square
    8Fsc
    Divisor
    1702
    1728
    1888
    2270
    PAL Fosc (MHz)
    26602
    270
    295
    35468
    Divisor
    1364
    1716
    1560
    1820
    NTSC Fosc (MHz)
    21476
    270
    24546
    28636
    CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL
    Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL
    6Fsc frequencies do not yield integer divisors
    Divisor does not include d 2 block
    Connection Diagram
    EL4585 SO P-DIP Packages
    4585 – 17
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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