參數(shù)資料
型號: EL4585CS-T7
廠商: ELANTEC
元件分類: XO, clock
英文描述: Horizontal Genlock, 8FSC
中文描述: 36 MHz, VIDEO CLOCK GENERATOR, PDSO16
封裝: SO-16
文件頁數(shù): 2/16頁
文件大?。?/td> 262K
代理商: EL4585CS-T7
EL4585C
Horizontal Genlock 8 FSC
Choosing Loop Filter
Components
The PLL VCO and loop filter can be described
as
4585 – 13
Where
Kdephase detector gain in Arad
F(s)eloop filter impedance in VA
KVCOeVCO gain in radsV
NeTotal internal or external divisor (see 3 be-
low)
It can be shown that for the loop filter shown
below
C3 e
KdKVCO
N
0n2
C4 e
C3
10
R3 e
2N
g
0n
KdKVCO
Where
0neloop filter bandwidth and geloop
filter damping factor
1 Kd e 300mA2qrad e 477e-5Arad for the
EL4585C
2 The loop bandwidth should be about H-sync
frequency20 and the damping ratio should be
1 for optimum performance For our example
0ne15734kHz20e787 Hz
5000 radS
3 N e 910x2 e 1820 from table 1
N e
FVCO
FHsync
e
28636M
1573426k
e
1820 e 910x2
4 KVCO represents how much the VCO frequen-
cy changes for each volt applied at the control
pin It is assumed (but probably isn’t) linear
about the lock point (25V) Its value depends
on the VCO configuration and the varactor
transfer function CveF(VC) where VC is the re-
verse bias control voltage and CV is varactor ca-
pacitance Since F(VC) is nonlinear it is probably
best to build the VCO and measure KVCO about
25V The results of one such measurement are
shown below The slope of the curve is deter-
mined by linear regression techniques and equals
KVCO For our example KVCOe906 MradsV
FOSC vs VC LCVCO
4585 – 14
5 Now we can solve for C3 C4 and R3
C3 e
KdKVCO
N
0n2
e
(477eb5)(906e6)
(1820)(5000)2
e
001
mF
C4 e
C3
10
e
0001
mF
R3 e
2N
g
0n
KdKVCO
e
(2)(1820)(1)(5000)
(477eb5)(906e6)
e
421k
X
We choose R3e43kX for convenience
6 Notice R2 has little effect on the loop filter de-
sign R2 should be large around 100k and can
be adjusted to compensate for any static phase
error Ti at lock but if made too large will
slow loop response If R2 is made smaller Ti
(see timing diagrams) increases and if R2 in-
10
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