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參數(shù)資料
| 型號： | EL4543IL-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 0K |
| 描述： | IC DRVR TWISTED TRPL DIFF 20-QFN |
| 標準包裝： | 1,000 |
| 應(yīng)用： | 驅(qū)動器 |
| 輸出類型： | 差分 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 350MHz |
| 轉(zhuǎn)換速率： | 1000 V/µs |
| 電流 - 電源： | 14.5mA |
| 電流 - 輸出 / 通道： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 12 V，±2.5 V ~ 6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
13
FN7325.11
September 13, 2007
Disable and Power Down
The EL4543 provides an enable disable function which
powers down, logic input high, in 900ns and powers up, logic
input low, in 212ns. Disabled the amplifiers supply current is
reduced to 1.8mA (Positive Supply) and 0mA (Negative
Supply). Note that Enable/Disable threshold is a linear
function of the supply voltage levels. The Enable/Disable
threshold voltage level is compatible with standard
TTL/CMOS and referenced to the lowest supply potential.
Proper Layout Technique
A critical concern with any PCB layout is the establishment
of a “healthy” ground plane. It is imperative to provide
ground planes terminated close to inputs to minimize input
capacitance. Additionally, the ground plane can be
selectively removed from inputs to prevent load and supply
currents from flowing near the input nodes.
In general the following guidelines apply to all PCB layout:
Keep all traces as short as possible.
Keep power supply bypass components as close to the
chip as possible - extremely close.
Create a healthy ground with low impedance and
continuous ground pathways available to all grounded
components board-wide.
In high frequency applications on multi-level boards try to
keep one level of board with continuous ground plane and
minimum via cutouts - providing it is affordable.
Provide extremely short loops from power pin to ground.
If it is affordable, a ferrite bead is always of benefit to
isolate device from Power Supply noise and the rest of the
circuit from the noise of the device.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL4543 drive capability is ultimately limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below TJMAX
(125°C). It is necessary to calculate the power dissipation for
a given application prior to selecting package type. Power
dissipation may be calculated:
where:
VS is the total power supply to the EL4543 (from VS+ to VS-)
ISMAX = Maximum quiescent supply current per channel
ΔVO = Maximum differential output voltage of the
application
RLD = Differential load resistance
ILOAD = Load current
Having obtained the application's power dissipation, the
maximum junction temperature can be calculated:
where:
TJMAX is the maximum junction temperature (125°C)
TMAX is the maximum ambient operating temperature
PD is the power dissipation calculated above
θ
JA is the thermal resistance, junction to ambient, of the
application (package + PCB combination). Refer to the
Package Power Dissipation curves.
Note:
For the QFN package, the thermal pad is internally
connected to VS- and may only be grounded in
applications where a single supply is used and VS- is
returned to ground. In applications where VS- is tied to a
negative voltage the thermal pad must also be connected
to the same negative voltage.
Application Circuit
Video Transmission Along CAT5 Cable
VGA input RGB plus sync is connected with 75
Ω termination
to the inputs of the EL4543. Single-ended RGB video is
converted to differential mode signals with HSYNC and
VSYNC encoded on the common-mode of the three
differential signals, respectively. The 50
Ω output-terminated
EL4543 drives the differential RGB with sync encoded
common-mode to CAT5 twisted pair cables. Note this
system, without signal frequency equalization, will
satisfactorily transmit along up to 200ft of CAT5 twisted-pair.
For longer cable lengths, frequency and gain equalization to
compensate for signal degradation is recommended
(EL9110) and a delay line technology (EL9115) to adjust for
phase mismatch between signals at the receiving end.
PD
3
V
S
I
SMAX
V
S
ΔV
O
R
LD
------------
×
+
×
×
=
(EQ. 1)
T
JMAX
T
MAX
Θ
JA
PD
×
+
=
(EQ. 2)
EL4543
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