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參數(shù)資料
| 型號(hào)： | EL4093CSZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO AMP 300MHZ 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 電流反饋 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 300MHz |
| 轉(zhuǎn)換速率： | 1500 V/µs |
| 電流 - 電源： | 9.5mA |
| 電流 - 輸出 / 通道： | 100mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
10
With RF = 750Ω, a GBWP of 310kHz is obtained. Note
however that this is the small signal GBWP. As mentioned
earlier, the sample and hold has special boost circuits built in
which provides ±8.5mA of charge current during full slew.
These boost circuits turn on when the S/H input differential
voltage exceeds ±50mV. When the boosters are turned on,
gm1 greatly increases and the circuit becomes nonlinear.
Thus some stability issues are associated with the boosters,
and they will be addressed in a later section.
Charge Injection and Hold Step
Charge injection refers to the charge transferred to the hold
capacitor when switching to the HOLD mode. The charge
should ideally be 0, but due to stray capacitive coupling and
other effects, is typically 0.1pC in the EL4093. This charge
changes the hold capacitor voltage by
ΔV = ΔQ/CHOLD, and
this
ΔV is multiplied by the output stage transconductance
(gm2) to produce a change in S/H output current. This last
quantity is listed as the spec
ΔISTEP, and is calculated using
the following:
For CHOLD = 2.2nF and gm2 = 1/(500Ω), ΔISTEP has a
typical value of 100nA. This change in S/H output current
flows through RF, shifting the CFA output voltage. However,
as we shall soon see, this shift is negligible. Assuming
RF =750Ω, ΔISTEP is impressed across RF to give
(750
Ω)(100nA) = 0.08mV of change at the CFA output.
Droop Rate
When the S/H amplifier is in HOLD mode, there is a small
current that leaks from the switch into the hold capacitor.
This quantity is termed the droop current, and is typically
10nA in the EL4093. This droop current produces a ramp in
the hold capacitor voltage, which in turn produces a similar
effect at the CFA output. The Droop Rate at the CFA output
can be found using the equation below:
Assuming RF = 750Ω and CHOLD = 2.2nF, the drift in the
CFA output due to droop current is about 7V/s. Recall that
in NTSC applications, there is about 60s between autozero
periods. Thus there is 7V/s(60s) = 0.4mV, or less than
0.1 IRE, of drift over each NTSC scan line. This drift is
negligible in most applications.
Choice of Hold Capacitor
The EL4093 has been designed to work with a hold
capacitor of 2.2nF. With this value of CHOLD, the droop rate
and hold step are negligibly small for most applications. In
addition, with the special boost circuits inside the S/H, fast
acquisition is possible even using a hold capacitor of this
size. Figure 5 shows the input and output of the DC-restored
amplifier while the S/H is in sample mode. Applying a +1V
step to the non-inverting input of the CFA, the output of the
CFA jumps to +2V. The S/H, however, then tries to autozero
the system by driving the CFA output back to the reference
voltage. Since the input differential across the S/H is initially
+2V, the boost circuits turn on and supply 8.5mA of charge
current to the hold capacitor. The boost circuit remains on
until the CFA output has come to within 50mV of the
reference. Note that this event took only 320ns; settling to
within 1% of the final value takes another 2s. Thus for a 1V
input step, acquisition takes only one to two NTSC scan
lines.
FIGURE 4.
ΔI
SEP
ΔQ
CHOLD
--------------------
gm2
×
=
Droop
IDROOP
CHOLD
---------------------- gm2
RF
×
()
=
EL4093
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