參數(shù)資料
型號： EDX5116ADSE-4D-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁數(shù)： 1/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE-4D-E
Doc. No. E1033E30 (Ver. 3.0)
Date Published September 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007
Overview
The EDX5116ADSE is a 512M bits XDR
DRAM organized
as 32M words
×
16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
nology permits 4000/3200 Mb/s transfer rates while using
conventional system and board design technologies. XDR
DRAM devices are capable of sustained data transfers of
8000/6400 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
It is packaged in 104-ball FBGA compatible with Rambus
XDR DRAM pin configuration.
Features
Highest pin bandwidth available
4000/3200 Mb/s Octal Data Rate (ODR) Signaling
Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
8000/6400 MB/s sustained data rate
Eight banks: bank-interleaved transactions at full
bandwidth
Dynamic request scheduling
Early-read-after-write support for maximum efficiency
Zero overhead refresh
Dynamic width control
EDX5116ADSE supports
×
16,
×
8 and
×
4 mode
Low latency
2.0/2.5 ns request packets
Point-to-point data interconnect for fastest possible
flight time
Support for low-latency, fast-cycle cores
Low power
1.8V Vdd
Programmable small-swing I/O signaling (DRSL)
Low power PLL/DLL design
Powerdown self-refresh support
Per pin I/O powerdown for narrow-width operation
Pin Configuration
7
6
4
3
2
1
DQ7
DQN7
DQN5
VDD
GND
RQ3
VDD
GND
DQN3
VDQ1
GND
RQ11
RQ10
GND
VDD
RQ9
RQ8
VDD
GND
RQ7
RQ6
VDD
CFM
CFMN
RQ4
VREF
GND
RQ5
RQ2
GND
VDD
RQ3
RQ0
GND
RQ1
RST
GGND
SD1
SCK
CMD
DG2
DQN2
DQN0
CMD
GND
VTERM
VDD
DQ6
DQN6
DQN4
GND
DQ4
DQ1
G
F
E
D
C
A
M
L
K
J
H
C
Row
A8
A16
E
F
H
J
K
L
5
6
7
8
9
10
11
1
2
3
4
DQN9
DQ9
DDQ5
VTVDD
VDD
VDD
GND
VTEDQN1
GND
RQ10
RQ11
GND
GND
VDD
SDI
GND
RQ0
GND
VTEDQ3
DQN8
DQ8
DQN4
VDD
GND
VTERM
G
D
C
B
A
DQ4
Top view of package
CFM
CFMN
GND
VDD
VDD
GND
GND
RSRV
RSRV
VDD
GND
DQN2
DQ2
DQN14
VDD
GND
GND
DQ14
DQN3
DQ3
DQN15
VDD
GND
GND
DQ15
12
13
14
15
16
DQSD0
DDQ0
DGND
VDD
SCK
RQ9
RQ8
VDD
GND
VDD
GND
RST
SDO
GND
DQN12
DQ12
DQN0
DQ0
RQ7
RQ6
VDD
VREF
RQ5
VDD
DQN6
DQ6
DQN10
DQ10
VDD
DQN7
DQ7
DQN11
DQ11
GND
GND
GND
VDD
VDD
512M bits XDR
DRAM
EDX5116ADSE (32M words
×
16 bits)
DATA SHEET
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