參數(shù)資料
型號: EDI9F81025C
英文描述: 2x512Kx8 Static RAM CMOS, Module(2x512Kx8 CMOS靜態(tài)RAM模塊)
中文描述: 2x512Kx8靜態(tài)RAM的CMOS模塊(2x512Kx8的CMOS靜態(tài)內(nèi)存模塊)
文件頁數(shù): 1/6頁
文件大?。?/td> 91K
代理商: EDI9F81025C
EDI9F81025C
2x512Kx8 SRAM Module
1
EDI9F81025C Rev. 4.0 4/96 ECO #7470
Features
2x512Kx8 bit CMOS Static
Random Access Memory
Access Times: 70, 85, and 100ns
Common Address and Data Pins
Data Retention Function (EDI9F81025LP)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
36 Lead SOIC Module, No. 198
Single +5V (
±10%) Supply Operation
2x512Kx8 Static RAM
CMOS, Module
The EDI9F81025C is an 8 megabit CMOS Static RAM based on
two 512Kx8 Static RAMs mounted on a multi-layered epoxy
laminate (FR4) substrate.
The EDI9F81025C is organized as two separate banks of 512Kx8
Random Access Memory, with common address and data pins to
minimize module size. It is offered with access times of 70, 85, and
100ns.
It is also available as EDI9F81025LP, which features Low Power
and Battery Back-up Data Retention.
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous, the EDI9F81025C requires
no clocks or refreshing for operation.
Pin Configurations and Block Diagram
A-A18
Address Inputs
E-E1
Chip Enable
W
Write Enable
G
Output Enable
DQ-DQ7
Common Data Input/Output
VCC
Power (+5V
±10%)
VSS
Ground
NC
No Connection
Pin Names
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
DQ
DQ1
DQ2
VSS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VCC
NC
A15
A17
W
A13
A8
A9
A11
G
A10
E1
E
DQ7
DQ6
DQ5
DQ4
DQ3
A-A18
W
G
E
E1
DQ-DQ7
512Kx8
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX: 01276 473748
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