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參數(shù)資料
| 型號： | EDI88512CA45N36I |
| 英文描述： | 200MHz Slew Enhanced VFA; Temperature Range: -40°C to 85°C; Package: 16-QSOP T&R |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 152K |
| 代理商： | EDI88512CA45N36I |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
tAVQX
tAVQV
tAVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA I/O
READ CYCLE 2 (WE HIGH)
tAVQV
tELQV
tGLQV
tELQX
tSHQV
tSHQX
tGLQX
tAVAV
tEHQZ
tGHQZ
OE
CS2
tSLQZ
CS1
WS32K32-XHX
FIG. 2
TIMING WAVEFORM - READ CYCLE
FIG. 4
WRITE CYCLE2
FIG. 3
WRITE CYCLE 1
ADDRESS
DATA IN
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
tWLEH
tEHAX
tELEH
tDVEH
tEHDX
tAVAV
DATA VALID
WE
CS1
tAVEL
CS2
ADDRESS
DATA IN
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
tAVWH
tELWH
tWHAX
tWLWH
tDVWH
tWLQZ
tWHQX
tAVWL
tWHDX
tAVAV
DATA VALID
HIGH Z
WE
tSHWH
CS1
DATA OUT
CS2
WRITE CYCLE 3
ADDRESS
DATA IN
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
tWLSL
tSLAX
tSHSL
tDVSL
tSLDX
tAVAV
DATA VALID
WE
CS1
tAVSH
CS2
相關PDF資料 |
PDF描述 |
|---|---|
| EDI88512CA45N36M | 200MHz Slew Enhanced VFA; Temperature Range: -40°C to 85°C; Package: 16-QSOP T&R |
| EDI88512CA45NB | 400MHz Slew Enhanced VFA; Temperature Range: -40°C to 85°C; Package: 16-QSOP |
| EDI88512CA45NC | 400MHz Slew Enhanced VFA; Temperature Range: -40°C to 85°C; Package: 16-QSOP T&R |
| EDI88512CA55TM | 12MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Input-Output Buffers; Temperature Range: -40°C to 85°C; Package: 24-TSSOP |
| EDI88512LPA17B32B | 12MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Input-Output Buffers; Temperature Range: -40°C to 85°C; Package: 24-TSSOP T&R |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDI88512CA45N36M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA45NB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA45NC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA45NI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| EDI88512CA45NM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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