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參數(shù)資料
| 型號(hào)： | EDI2GG464128V-D |
| 英文描述： | SSRAM Modules |
| 中文描述： | 的SSRAM模塊 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 243K |
| 代理商： | EDI2GG464128V-D |
EDI2GG464128V
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
G\
GW\
E1\
GW\
G\
E\
DQ
GW\
G\
E\
DQ
GW\
G\
E\
DQ
GW\
G\
E\
DQ
E3\
GW\
G\
E\
DQ
GW\
G\
E\
DQ
GW\
G\
E\
DQ
GW\
G\
E\
DQ
E2\
E4\
CLK
A0-16
128Kx64
DQ0-63
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
Input/Output Bus
A0-15
Address Bus
E1-4\
Synchronous Bank Enables
CLK
Array Clock
GW\
Synchronous Global Write
Enable
G\
Asynchronous Output Enable
Vcc
3.3V Power Supply
Vss
Ground
NC
No Connect
PIN NAMES
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 5, 7, 9, 13, 15,
A0-15
Input
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
17, 19, 20, 23, 18,
Synchronous
The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
16, 14, 10, 8, 6
38
GW\
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines
Synchronous
and must meet the setup and hold times around the rising edge of CLK.
27
CLK
Input
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising
Synchronous
edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
36, 32
E1, E2\
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
35, 31
E3\, E4\
Synchronous
37
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth
byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
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